1. Manuals
  2. Brands
  3. Themis Manuals
  4. Motherboard
  5. USPIIi-1v
  6. Hardware manual

Themis USPIIi-1v Hardware Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
USPIIi-1v
Hardware Manual
Revision B4

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the USPIIi-1v and is the answer not in the manual?

Questions and answers

Related Manuals for Themis USPIIi-1v

Summary of Contents for Themis USPIIi-1v

  • Page 1 USPIIi-1v Hardware Manual Revision B4...
  • Page 3 USPIIi-1v Hardware Manual Version B4 — December 2001 Themis Computer—Americas and Pacific Rim Themis Computer—Rest of World 3185 Laurelview Court 20 rue du Tour de l’Eau Fremont, CA 94538 38400 Saint Martin d’Hères, France Phone (510) 252-0870 Phone +33 476 59 60 46...
  • Page 4 Themis Computer assumes no responsibility for inaccuracies. Themis Computer retains the right to make changes to this publication at any time without prior notice. Themis Computer does not assume any liability arising from the application or use of this publication or the product(s) described herein.
  • Page 5 Version Revision History Version B4 December 2001 Replaced Universe II with Universe IIB throughout manual. Corrected misspellings throughout manual. Reenforced definition of backplane reset on pages 2-2 and B-2. Defined non-standard signal for P2 pin B3 in Table A-2, page A-3. Reversed Serial Port C and D callouts, pages C-3, C-4, and D-5.
  • Page 6 USPIIi-1v User’s Manual Themis Computer...

  • Page 7: Table Of Contents

    Chapter Overview ....................Related References ....................Installation ......................Determine Board Type and Configuration ............Configuration ......................Backplane Jumper Settings ..................Installing The USPIIi-1v Paddle Board ..............Attaching Cables to Peripheral Devices ..............2.5.1 Console Port (TTYA) ................2.5.2 Keyboard and Mouse ................
  • Page 8 4.1.12 TOD and NVRAM................. Memory Subsystem ....................PMC Carrier Subsystem ..................OpenBoot PROM....................Universe-IIB Description ..................Features ........................USPIIi-1v and the Universe IIB PCI Interface ............VMEbus Interface....................5.3.1 VMEbus Configuration................5.3.2 Universe IIB as the VMEbus Slave ............5.3.3 Universe IIB as the VMEbus Master .............

  • Page 9: Introduction

    7.3.4 3-Level Watchdog Resets ..............7.3.5 Software POR ..................7.3.6 Software XIR ..................UltraSPARC-IIi Reset Control Register ..............USPIIi-1v Reset Tree Diagram................Connector Pinouts, LEDs, Switches ..............Introduction......................Baseboard Front Panel ................... A.2.1 Baseboard VME P1 ................A.2.2 Baseboard VME P2 ................
  • Page 10 USPIIi-1v Hardware Manual A.2.10 Push-Button RESET ................A-13 I/O Board ....................... A-14 A.3.1 I/O Board VME P2 ................A-14 A.3.2 Serial Port C (TTYC or Console) and Serial Port D (TTYD or Aux Port) A- A.3.3 Parallel Port.................... A-18 A.3.4 RJ45 Ethernet B Connector ..............
  • Page 11 Table 3-2. Memory Specification ......................3-4 Table 3-3. I/O Sub-system Specification ....................3-5 Table 3-4. Auxiliary Functions Specifications ..................3-6 Table 3-5. USPIIi-1v Operating Environmental Specifications ............. 3-7 Table 3-6. USPIIi-1v Non-operating Environmental Specifications............3-7 Table 3-7. Estimated Power Requirements..................... 3-8 Table 4-1.
  • Page 12 USPIIi-1v Hardware Manual Table 6-4. Watchdog POR Enable/Disable .................... 6-2 Table 6-5. Watchdog Enable/Disable ..................... 6-3 Table 7-1. UltraSPARC-IIi Reset_Control Register................7-5 Table A-1. Baseboard VME P1 Pinout....................A-2 Table A-2. Baseboard VME P2 Connector in PS/2 Mode..............A-3 Table A-3. Baseboard VME P2 Connector in Sun Mode..............A-4 Table A-4.
  • Page 13 List of Figures Figure 3-1. USPIIi-1v Baseboard Block Diagram.................. 3-3 Figure 4-1. Memory Sub-System Topology ................... 4-5 Figure 5-1. Universe IIB Architectural Diagram..................5-4 Figure 5-2. Address Translation for VMEbus to PCI Bus Transfers............5-9 Figure 5-3. Address Translation for PCI Bus to VMEbus Transfers............ 5-10 Figure 5-4.
  • Page 14 USPIIi-1v Hardware Manual Figure B-2. I/O Board Jumper Locations ....................B-5 Figure B-3. Baseboard Component Side Solder Bead Locations ............B-8 Figure B-4. Baseboard Solder Side Solder Bead Locations ..............B-8 Figure B-5. I/O Board Solder Side Solder Beads .................B-10 Figure C-1. Single Slot Front Panel......................C-2 Figure C-2.

  • Page 15: How To Use This Manual

    USPIIi-1v and assumes the Open Boot Program (OBP) code is installed in the system flash. If you intend to operate the USPIIi-1v with an operating system other than Solaris, such as VxWorks or other real-time kernel, please consult the appropriate documentation supplements accompanying your OS or kernel software.

  • Page 16: Product Warranty And Registration

    Please review the Themis Computer warranty and complete the product registration card delivered with your USPIIi-1v board(s). Return of the registration card is not required to activate your product warranty but, by registering your USPIIi-1v, Themis Computer will be better able to provide you with timely updated information and product enhancement notifications.

  • Page 17: How To Start Quickly

    • A second Paddle Board, Themis Part Number 105581. This paddle board must be connected behind the second slot occupied by the USPIIi-1v board • A second 68 pin, SCSI-3 ribbon cable for the second paddle board SCSI (SCSI B); Themis Part Number 108432.

  • Page 18: Chapter Overview

    • Chapter 2, "Installation," provides instructions on the installation and configuration of the USPIIi-1v for your particular environment and application. The information contained in this chapter is mandatory for the correct operation of the USPIIi-1v. This chapter should be read in its entirety before use of the board.
  • Page 19 • Symbios SYM53C876 SCSI I/O Processor Data Manual, Version 3.0, 1996 Sun documents are available for download on www.sun.com or docs.sun.com. Hardcopies can be ordered on the the catalog section of the SunExpress™ Internet site at www.sun.com/sunexpress. Non-Sun documents are available from their respective vendor’s Web site. Themis Computer...
  • Page 20 USPIIi-1v Hardware Manual Themis Computer...

  • Page 21: Installation

    PS/2-type keyboard and mouse; Sun configuration means that Sun type 5 keyboard and mouse can be installed. USPIIi-1v and -1v/2p boards are only available in PS/2 mode. To determine the mode configured on USPIIi-1v/2c and -1v/3 boards, check the position of jumper JP3304 on the baseboard (the slot #1 board).

  • Page 22: Configuration

    PMC Carrier board to PMC #1, as opposed to routing 32 bits of User I/O to PMC #1 and 32 bits of User I/O to PMC #2. If the default jumper settings meet your requirements you are now ready to install the USPIIi-1v in a standard VME chassis.

  • Page 23: Installing The Uspiii-1V Paddle Board

    It provides connectors for Serial Ports, Ethernet MII and SCSI. • For the USPIIi-1v/1 and USPII-1v/2p, only one paddle board can be installed. It is part of the single slot integration kit, INT-KIT-USPIIi-1v/1-VME. This paddle board must be installed at the rear of the P2 backplane, behind the position occupied by the baseboard (for the USPIIi-1v/2p, a second VME slot is occupied by the PMC extension carrier).

  • Page 24: Attaching Cables To Peripheral Devices

    Note — If the USPIIi-1v is used with Creator Graphics, it is not mandatory to attach it to a serial terminal if already connected to PS/2 or Sun keyboard/mouse. In this case, software will automatically use this keyboard for input and the Graphics port for output.

  • Page 25: Keyboard And Mouse

    SCSI A and B Themis Computer provides adapter cables for SCSI A or B with conversion to standard 68 pin, 0.050 inch, male SCSI connectors. Attach cable 108712 to the desired SCSI connection (SCSI A or SCSI B) on the front panel min-din 68 connector labelled either “SCSI A”...

  • Page 26: Creator Graphics Card

    Note — Creator Graphics must be used in conjunction with a PS/2 or Sun keyboard and mouse. If the latter are not attached to the USPIIi-1v board prior to power on, OpenBoot will redirect its text output to the serial console and not to Creator Graphics...

  • Page 27: Specification

    • USPIIi-1v/3, “USPIIi-1v with Graphics, Expanded I/O, and PMC Carrier Board” provides the all the features in the “USPIIi-1v with Graphics and Expanded I/O” and the “USPIIi-1v with a PMC Carrier Board”. The optional Creator Graphics card and Expanded I/O are located in the second slot. The PMC Carrier board is located in the third slot.

  • Page 28: I/O Board And Creator Graphics

    3.1.4 Paddle Board A single slot, P2 paddle board is available for the USPIIi-1v baseboard and for the USPIIi-1v I/O board. The same paddle board design used for the baseboard is used for the I/O board. When used in conjunction with the baseboard, the paddle board provides the user with connections for MII A, Serial B, and SCSI A.

  • Page 29: Block Diagram

    32-bit PCI 32-bit PCI Ethernet A Exp. Conn PCIOs PCI-VME E-Bus SCSI Expansion Exp. Bridge Keyboard Flash Super I/O Parallel Slot Slot Slot Serial 2nd & 3rd Slot Exp. * via I/O Board Figure 3-1. USPIIi-1v Baseboard Block Diagram Themis Computer...

  • Page 30: System Specification

    USPIIi-1v Hardware Manual System Specification 3.2.1 Processor & Memory Subsystems Below are the processor and memory subsection specifications. Table 3-1. Processor Specifications Feature/Function Specifications Processor UltraSPARC-IIi Processor Speed Grade 1 - 360 MHz Grade 2 - 440 MHz Performance 18.3 SPECint95 @ 440 MHz w/ 2 MB cache (estimate) 20.4 SPECfp95 @ 440 MHz w/ 2 MB cache (estimate)

  • Page 31: I/O Subsystem

    Slot 2 P2 40 MB/s PMC Expansion, 32-bit/33MHz Slot 2: Slot 3: Three PMC Slots in a single PMC1:FP/P2 PMC1: FP/P2 VME slot PMC2: FP/P2 PMC2: FP/P2 PMC3: FP PMC3: FP Creator Graphics Slot 2 Slot 2 (Optional) (Optional) Themis Computer...

  • Page 32: Auxiliary Functions

    USPIIi-1v Hardware Manual Table 3-3. I/O Sub-system Specification Triple Slot Dual Slot Dual Slot (Baseboard, (Baseboard, Single Slot (Baseboard and Creator Function Creator (Baseboard) PMC Carrier Graphics, I/O Graphics and Board) Board, and PMC I/O Board) Carrier Board) Audio Line In...

  • Page 33: Environmental Specification

    When measuring the operating environment air temperature for the USPIIi-1v, measure the air temperature as close to the air intake port on the enclosure as possible. Although the thermal characteristics of the USPIIi-1v are quite good, the maximum air flow should be across the USPIIi-1v board processor section.

  • Page 34: Estimated Power Requirements

    USPIIi-1v Hardware Manual Estimated Power Requirements Table 3-7. Estimated Power Requirements Configuration Watts Dissipation (USPIIi-1v/1 with (typical) 360/440 MHz processor) 128 MBytes memory 32/34 Watts 256 MBytes memory 34/36 Watts 1024 MBytes memory 35/37 Watts Themis Computer...

  • Page 35: Hardware Overview

    4Hardware Overview Major Components The following sections provide a description of the major of the USPIIi-1v. More detailed explanations of certain subsystems is provided in later sections and chapters. 4.1.1 SME UltraSPARC-IIi Processor and Cache The Central Processor for the USPIIi-1v is the UltraSPARC-IIi (SME: SME1430). There are two versions of CPU available, the UltraSPARC IIi-360 and the UltraSPARC IIi-440.

  • Page 36: Sme Advanced Pci Bridge (Apb)

    (2), +5V, 32-bit, 33MHz PCI buses into one +3.3V, 32-bit, 66 MHz PCI bus that interface directly with the UltraSPARC-IIi. The 66 MHz PCI-to-CPU can achieve a peak bandwidth of 2 GBits/sec. Within the USPIIi-1v, the two (2), 33 MHz PCI busses are referred to as PCIA and PCIB. 4.1.4...

  • Page 37: Sme Pci I/O Controller

    4.1.8 FPGA The FPGA device on the USPIIi-1v is the Altera EPF8820. It resides on the EBus2 of the baseboard PCI I/O ASICs. Physically, the FPGA is located on the baseboard. The FPGA implements a voltage monitor, boot address decoder, a three-level watchdog timer, and the SYSTEM_OK_LED register. At boot-up the FPGA self loads from a serial EPROM (Altera EPC1213PC8) to program itself for these features.

  • Page 38: Tod And Nvram

    Memory Subsystem The USPIIi-1v supports up to two coplanar memory modules of either 64 MB, 128 MB, 256 MB or 512 MB each. The modules may be combined to provide 64 MB, 128 MB, 256 MB, 512 MB or 1024 MB in a single slot configuration.

  • Page 39: Pmc Carrier Subsystem

    The PMC Carrier Board subsystem supports up to three (3) standard PMC boards in either the second or third slot of the USPIIi-1v product configuration. If the I/O board or Creator Graphics card is included in the product configuration (USPIIi-1v/3), the PMC carrier board is physically located in the third slot. Otherwise, the PMC Carrier board is located in the second slot (USPIIi-1v/2p).
  • Page 40 FORTH language interpreter. Entry into the FORTH Toolkit is signified by the “ok” prompt. For more information on the OBP please refer to the OpenBoot Command Reference from Sun Microsystems and to the “USPIIi-1v Software Manual”. Themis Computer...

  • Page 41: Universe-Iib Description

    • Support for RMW cycles and lock cycles This chapter is intended to outline the VMEbus to PCI Bus interface on the USPIIi-1v. If more detailed information is need, please refer to the Tundra “Universe II User’s Manual”, Spring 1998.

  • Page 42: Uspiii-1V And The Universe Iib Pci Interface

    USPIIi-1v Hardware Manual USPIIi-1v and the Universe IIB PCI Interface The following table lists some of the PCI signals of the USPIIi-1v to the Universe IIB’s PCI interface. Table 5-1. Universe IIB PCI Interface Pins USPIIi-1v Universe IIB Pins Primary PCI Bus...

  • Page 43: Universe Iib As The Vmebus Master

    The DMA Channel requests the VMEbus Master Interface when: • the DMAFIFO has 64 bytes available when reading from the VMEbus • the DMAFIFO has 64 bytes in its FIFO when writing to the VMEbus • the DMA block is complete. Themis Computer...

  • Page 44: Vmebus First Slot Detector

    As defined by the VME64 specification, the Universe IIB samples the BG3IN# right after the reset to determine if the USPIIi-1v resides in slot 1. If the BG3IN# is sampled low right after the reset, the USPIIi-1v board becomes the SYSCON. Otherwise the SYSCON Module of the Universe IIB is disabled. The software can set or clear the SYSCON bit the MISC_CTL register of the Universe IIB.

  • Page 45: Automatic Slot Identification

    – A bus timer – An IACK Daisy Chain Driver (DCD). The USPIIi-1v supports Round-Robin arbitration. The VMEbus arbitrator time out is also controlled by the MISC_CNT register described above. The timer may be set to either 16 µ , 256 µ...

  • Page 46: Universe Iib's Hardware Power -Up Options

    Address VA[31..1] and VMEbus Data VD[31..27]. Table 5-3, "Address Translation for PCI Bus to VMEbus Transfers," on page 5-10 for the Universe IIB’s power up options on the USPIIi-1v. The Universe IIB is automatically configured at power up to operate in the default configuration listed in Table 5-3, "Universe IIB Power Up Options,"...

  • Page 47: Slave Image Programming

    PCI Bus Address Space: 0 = Memory; 1 = I/O Power-up Options All other bits are Read 0. Slave Image Programming The Universe II recognizes two types of accesses on its bus interfaces: accesses destined for the other bus and accesses decoded for its own register space. Themis Computer...

  • Page 48: Vme Slave Images

    USPIIi-1v Hardware Manual 5.4.1 VME Slave Images A VMEbus slave image is used to access the resources of the PCI bus when the Universe II is not the VMEbus master. The user may control the type of accesses by programming specific attributes of the VMEbus slave image.

  • Page 49: Pci Bus Target Images

    VMEbus and control to the type of access to the VMEbus. There are eight (0-7) standard PCI target images and one special PCI target image. The special PCI target image may be used for A16 and A24 transaction, freeing the other 8 images for standard A32 transactions. Themis Computer...

  • Page 50: Pci Bus Fields

    USPIIi-1v Hardware Manual 5.4.2.1 PCI Bus Fields Decoding for VMEbus accesses is based on the address and command information produced by a PCI bus master. The PCI Target Interface claims a cycle if there is an address match and if the command matches certain criteria.

  • Page 51: Table 5-10. Pci Bus Fields For Pci Bus Target Image

    I/O space, that is decoded using PCI address lines [31:26]. Its base address is aligned on 64 MB boundaries and no offsets are provided. Therefore, PCI address information is mapped directly to the VMEbus. The special PCI target image has a lower priority than any other PCI target image. 5-11 Themis Computer...

  • Page 52: Table 5-12. Pci Bus Fields For Special Pci Bus Target Image

    USPIIi-1v Hardware Manual The 64 MB space is divided into four (4), 16 MB spaces that are selected using AD[25:16]. For each region, the upper 64 KB map to VMEbus A16 space, while the remaining portion map to VMEbus A24 space. The addressing of this slave image is depicted in Figure 5-2 "Address Translation for VMEbus to PCI Bus...
  • Page 53 0 = Non-Privileged, 1 = Supervisor 07-02 BS [5..0] Base Address Specifies a 64 MB aligned base address for this 64 MB image Reserved PCI Bus Address Space 0 = PCI Bus Memory Space, 1 = PCI Bus I/O Space 5-13 Themis Computer...

  • Page 54: Figure 5-4. Memory Mapping In The Special Pci Target Image

    USPIIi-1v Hardware Manual BASE+0x400.0000 64 MB BASE+0x3FF.FFFF 16 MB BASE+0x300.0000 BASE+0x2FF.0000 BASE+0x200.0000 BASE+0x1FF.0000 BASE+0x100.0000 BASE+0x0FF.0000 BASE+0x000.0000 Figure 5-4. Memory Mapping in the Special PCI Target Image Universe IIB’s Interrupt and Interrupt Handler 5.5.1 VME and PCI Interrupters: For the VMEbus, the interrupt source can be mapped to any of the VMEbus interrupt output pins such as VIRQ#[7..0].

  • Page 55: Vmebus Interrupt Handling

    VMEbus, PCI bus, and control fields. There is one special PCI target image which is separate from the VMEbus, PCI bus, and the control fields (refer to Section 5.4, "Slave Image Programming," on page 5-7). 5-15 Themis Computer...

  • Page 56: Dma Controller

    USPIIi-1v Hardware Manual 5.5.6 DMA Controller The Universe IIB utilizes an internal DMA controller for high performance data transfer between the VMEbus and the PCI bus. Universe IIB’s parameters for the DMA transfer are software configurable. DMA operations between the source and destination bus are decoupled via the use of a single bidirectional FIFO (DMAFIFO).

  • Page 57: Fpga, Watchdog, Voltage And Temperature Sensors

    6.1.1 Introduction The FPGA device on the USPIIi-1v is the Altera EPF882 and resides on the EBus2 of the baseboard PCI I/O ASICs. Physically, the FPGA is located on the baseboard. The FPGA implements a voltage monitor, boot address decoder, a three-level watchdog timer, and the READY_LED register. At boot-up the FPGA self loads from a serial EPROM (Altera EPC1213PC8) to program itself for these features.

  • Page 58: 3-Level Watchdog

    The counter register and the status register are read-only while the limit register is read/write. Refer to the “USPIIi-1v Software Manual” for a description of the Watchdog Registers. Note — The 3-level watchdog implemented in the FPGA is entirely separate from the internal watchdog of the UltraSPARC-IIi.

  • Page 59: Power Management System

    6. FPGA, Watchdog, Voltage and Temperature Sensors When no watchdogs have expired the USPIIi-1v is in a ‘normal’ state. When the level 1 watchdog expires, a maskable interrupt is sent to the RIC. The USPIIi-1v is considered to be in a ‘warning’ state. Upon expiration, the level 2 watchdog issues a non-maskable XIR interrupt to the RIC.
  • Page 60 USPIIi-1v Hardware Manual Power Management System entering coping state will turn the front ALARM LED to amber. In failed state, the LED will turn RED and the POWER FAIL signal will be asserted on VME P2. See Appendix A.2.2, "Baseboard VME P2," and Appendix A.2.9, "LEDs." The POWER FAIL signal on P2 will also be asserted if VME ACFAIL is active.

  • Page 61: Temperature Sensor

    Two user defined temperatures are stored in the Dallas DS1620’s NVRAM: temp-warning and temp-critical. These variables may be configured by through OBP extension variables (refer to the “USPIIi-1v Software Manual”). The settings of temp-critical and temp-warning are stored in the 8-bit TL and 8-bit TH registers of the DS1620.
  • Page 62 USPIIi-1v Hardware Manual Themis Computer...

  • Page 63: Resets

    7Resets Overview This chapter presents a brief discussion of the reset structure of the USPIIi-1v. The various types of resets, some possible reset sources, and reset effects are explained. Resets are used to force all or part of the system into a known state. A Reset is defined as any action or signal that places the UltraSPARC-IIi in Reset, Error, and Debug State (RED_State).

  • Page 64: Ultrasparc-Iii Reset Request Signals

    The UltraSPARC-IIi CPU will propagate this reset to all of the subsystems of the USPIIi-1v, including the E- Cache, FLASH, UPA64S, and through the Advanced PCI Bridge (APB) to PCI A and PCI B buses to all other devices.

  • Page 65: Software Initiated Reset (Sir)

    The UltraSPARC-IIi also accepts SYS_RESET_L from the FPGA. Part of the power management system, this signal will cause a reset of the USPIIi-1v, as explained below (refer to Section 7.3.2, "Power Management Resets," on page 7-3).

  • Page 66: Vmebus Resets

    An incoming VMEbus may be enabled or disabled through the setting of jumper JP3901. If JP3901 is installed to 1-2 the USPIIi-1v may be reset from the VMEbus. If JP3901 is installed to 2-3 or left open, resets from the VMEbus will be disabled.

  • Page 67: Ultrasparc-Iii Reset Control Register

    Set if the last reset was due to the assertion of P_RESET_L R/W1C B_XIR Set if the last reset was due to the assertion of an X_Reset_L R/W1C Reserved 26:0 Reserved The highest priority reset source has its bit set. Only the bits marked with “*” are set. Themis Computer...

  • Page 68: Uspiii-1V Reset Tree Diagram

    SCSI ENET Universe IIB Figure 7-1. USPIIi-1v Reset Diagram 1. Internal to the UltraSPARC-IIi are the Watch Dog Reset (WDR) and Software Initiated Reset (SIR). These two resets are initiated within the processor core and effect only the processor Themis Computer...

  • Page 69: Aconnector Pinouts, Leds, Switches

    AConnector Pinouts, LEDs, Switches Introduction The following appendix provides the connector pinouts for the user interfaces on the USPIIi-1v as well as descriptions of other user interfaces such as LEDs and Switches. The baseboard, I/O Board, PMC Carrier Board, and Paddle Board connector pinouts are each presented as individual sections. For a diagram of the front panel I/O available on each board, refer to Appendix C, "Front Panel Diagrams."...

  • Page 70: Table A-1. Baseboard Vme P1 Pinout

    USPIIi-1v Hardware Manual Table A-1. Baseboard VME P1 Pinout Row A Row B Row C Signal Name Signal Name Signal Name VME D00 VME BBSY VME D08 VME D01 VME BCLR VME D09 VME D02 VME ACFAIL VME D10 VME D03...

  • Page 71: Baseboard Vme P2

    – HI TEMP: Asserted when Critical Temperature is reached (refer to 6.2, "Temperature Sensor," on page 6-5) – SW ALARM: User-defined. Asserted on a write access to address 0x1ff.f110.0000. Refer to the USPIIi-1v Software Manual. • Connector Type: VME32 (Top View)
  • Page 72 USPIIi-1v Hardware Manual Table A-2. Baseboard VME P2 Connector in PS/2 Mode (Continued) Row A Row B Row C Signal Name Signal Name Signal Name MII A TX EN SCSI A DAT<0> MII A TXD0 VME D16 SCSI A DAT<1>...

  • Page 73: Table A-3. Baseboard Vme P2 Connector In Sun Mode

    SCSI A PAR<1> This is part of the Automatic SCSI termination logic: SCSI A P2 signal will be forced to ground by the mating SCSI connector when attached. This will disable the active onboard SCSI terminator on the P2 side. Themis Computer...

  • Page 74: Scsi A And B

    USPIIi-1v Hardware Manual A.2.3 SCSI A and B • Connector Type: Honda Dual SCSI-3 (40 MB/sec) Connector, 68 Pin, 0.8 mm Pitch • Connector Part Number: HDRA-E68WILDT-SL SCSI Port B (J1101) SCSI Port A (J1102) Front View of PCB Figure A-3. Baseboard SCSI A and B Connector Orientation Table A-4.
  • Page 75 DAT<11> This is part of the Automatic SCSI termination logic: The SCSI FP signal will be forced to ground by the mating SCSI connector when attached. This will disable the active onboard SCSI terminator on the front side. Themis Computer...

  • Page 76: Rj45 Ethernet A Connector

    USPIIi-1v Hardware Manual A.2.4 RJ45 Ethernet A Connector • Connector Type: RJ-45 TPE Front View of PCB Figure A-4. Ethernet A Connector Orientation Table A-5. RJ45 Ethernet A Pinout Signal Name TXD+ TXD- RXD+ 4T_D3P 4T_D3P RXD- 4T_D4P 4T_D4P Themis Computer...

  • Page 77: Keyboard/Mouse Connector And Serial Port A (Ps/2 Mode Only

    Front View of PCB Figure A-5. Baseboard Console and Keyboard/Mouse Connector Orientation (PS/2 Mode) Table A-6. Baseboard Console and Keyboard/Mouse Pinout (PS/2 Mode) Pins Keyboard/Mouse Signal Names Pins Serial Port A Signal Names KB DATA KB CLK Mouse DATA Mouse CLK Themis Computer...

  • Page 78: Ps/2 Keyboard/Mouse Split Cable

    USPIIi-1v Hardware Manual A.2.6 PS/2 Keyboard/Mouse Split Cable PS/2 Mouse Connector Front Panel Connector PS/2 Keyboard Connector Figure A-6. PS/2 Keyboard/Mouse Split Cable Table A-7. PS/2 Keyboard/Mouse Split Cable Pinout Front Panel Keyboard/ Signal Name PS/2 Keyboard Pin PS/2 Mouse Pin...

  • Page 79: Serial Port A (Console) Adapter Cable (Ps/2 Mode Only

    Figure A-7. Serial Port Adapter Cable Table A-8. Serial Port A (Console) Adapter Cable Front Panel Serial Port A Signal Name Serial Port A Cable Pinout (Console) Pinout Miniature DB9, DB25 All unlisted pins on the DB25 connector are “No Connect.” A-11 Themis Computer...

  • Page 80: Keyboard/Mouse Connector And Serial Port A (Sun Mode Only

    Mouse. Therefore they are no longer available. The console port will be redirected to TTYC (I/O board front panel). The SUN keyboard/Mouse connects to the front panel console/TTYA port through a cable available from Themis (Micro SUB DB9 to DIN8. Part Number is 108783) • Connector Type: Two (2), stacked Mini-DB9 •...

  • Page 81: Leds

    Cause 3: Board reached Critical/Shutdown Temperature • The green “READY” LED is totally controlled by software. Refer to the USPIIi-1v Software Manual for more information. When OBP takes control of the board at power-on, one of its first instructions is to turn READY on.

  • Page 82: I/O Board

    For a diagram of the I/O Board front panel refer to Appendix C.3, "Baseboard, I/O Board, and Creator Graphics Front Panels." Caution — As VME P1 is not populated, the position occupied by the I/O board (position #2 on USPIIi-1v/ 2c and 1v/3) may require jumpering. Refer to Section 2.3, "Backplane Jumper Settings," on page 2-2 for more information A.3.1...
  • Page 83 This is part of the Automatic SCSI termination logic: The SCSI B P2 signal will be forced to ground by the mating SCSI connector when attached. This will disable the active onboard SCSI terminator on the P2 side. A-15 Themis Computer...

  • Page 84: Serial Port C (Ttyc Or Console) And Serial Port D (Ttyd Or Aux Port) A

    USPIIi-1v Hardware Manual A.3.2 Serial Port C (TTYC or Console) and Serial Port D (TTYD or Aux Port) In Sun mode, the two baseboard serial ports (ports A and B) are used by the keyboard and mouse logic, respectively. Therefore, serial Port C becomes the software console port (also know as TTYA) and serial Port D is the auxiliary port (TTYB).
  • Page 85 Table A-12. I/O Board TTY C AND TTY D Pinout Pins TTY C Signal Name Pins TTY D Signal Name TXC+ TXC+ CTS+ CTS+ TXD+ TXD+ RXD+ RXD+ RXC- RXC- RTS+ RTS+ DTR- DTR- DTR+ DTR+ TXC- TXC- A-17 Themis Computer...

  • Page 86: Parallel Port

    USPIIi-1v Hardware Manual A.3.3 Parallel Port • Connector Type: 0.050, 26 pin, Sub D, Amplimite Slimline Connector • Connector Part Number: AMP 750823-1 Front View of PCB Figure A-11. I/O Board Parallel Port Connector Orientation Table A-13. I/O Board Parallel Port Pinout...

  • Page 87: Rj45 Ethernet B Connector

    A.3.6 Creator Graphics Slot With the USPIIi-1v/2c and 1v/3, a Creator Graphics Card may be installed on the baseboard (UPA64S connector J4901). The card will occupy the second slot, adjacent to the I/O Board. Video signals are available on a standard DB13W3 connector. An additional circular DIN connector outputs synchronization signals to stereo displays.

  • Page 88: Pmc Carrier Board

    USPIIi-1v Hardware Manual PMC Carrier Board For a diagram of the PMC Board front panel refer to . A.4.1 PMC Carrier Board P1 Connector The P1 connector provides daisy-chaining of IACK and BG signals. There is no need to jumper those signals manually for the position occupied by the PMC carrier.
  • Page 89 A. Connector Pinouts, LEDs, Switches Table A-15. PMC Carrier Board VME P1 Pinout Row A Row B Row C Signal Name Signal Name Signal Name DAISY_CHAIN_IACK# DAISY_CHAIN_IACK# -12V +12V A-21 Themis Computer...

  • Page 90: Pmc Carrier Board Vme P2 Connector

    USPIIi-1v Hardware Manual A.4.2 PMC Carrier Board VME P2 Connector The VME P2 Connector of the PMC Carrier can contain either 64 user-defined signals from PMC slot #1, or 32 signals from PMC slot #1 and 32 from PMC slot #2.
  • Page 91 PMC IO C26 PMC IO A27 PMC IO C27 PMC IO A28 PMC IO C28 PMC IO A29 PMC IO C29 PMC IO A30 PMC IO C30 PMC IO A31 PMC IO C31 PMC IO A32 PMC IO C32 A-23 Themis Computer...

  • Page 92: Pmc Carrier Slot User I/O

    USPIIi-1v Hardware Manual A.4.3 PMC Carrier Slot User I/O This section provides the pinout of the 64 PMC User I/O signals that can be brought from PMC cards to the VME P2 connector of the PMC Carrier board. Also see Appendix A.4.2, "PMC Carrier Board VME P2 Connector,"...
  • Page 93 PMC IO A29 PMC IO C14 PMC IO C30 PMC IO A14 PMC IO A30 PMC IO C15 PMC IO C31 PMC IO A15 PMC IO A31 PMC IO C16 PMC IO C32 PMC IO A16 PMC IO A32 A-25 Themis Computer...

  • Page 94: Pmc Carrier Slot #1: 32 Bit User I/O Configuration

    USPIIi-1v Hardware Manual A.4.3.2 PMC Carrier Slot #1: 32 Bit User I/O Configuration Table A-18. PMC Carrier Slot #1 with 32 Bits of User I/O Pin Number Signal Pin Number Signal PMC IO C17 PMC IO A17 PMC IO C18...

  • Page 95: Pmc Carrier Slot #2: 32 Bit User I/O Configuration

    PMC IO A10 PMC IO C11 PMC IO A11 PMC IO C12 PMC IO A12 PMC IO C13 PMC IO A13 PMC IO C14 PMC IO A14 PMC IO C15 PMC IO A15 PMC IO C16 PMC IO A16 A-27 Themis Computer...

  • Page 96: Paddle Board

    USPIIi-1v Hardware Manual Paddle Board A.5.1 SCSI Connector • Connector Type: 68 Pin, Female, Shielded Subminature-D • Connector Part Number: AMP 787082-7 Front View of PCB Figure A-16. Paddle Board SCSI Connector Table A-20. Paddle Board SCSI Connector Pinout Signal Name...
  • Page 97 DAT11 This is part of the Automatic SCSI termination logic: SCSI P2 signal will be forced to ground by the mating SCSI connector when attached. This will disable the active onboard SCSI terminator on the P2 side. A-29 Themis Computer...

  • Page 98: Mii Connector

    USPIIi-1v Hardware Manual A.5.2 MII Connector • Connector Type: 40 Pin, Female, Subminiature-D • Connector Part Number: AMP 787170-4 Front View of PCB Figure A-17. Paddle Board MII Connector Table A-21. Paddle Board MII Connector Pinout Signal Name Signal Name...

  • Page 99: Table A-22. Paddle Board Db9 Connector Pinout

    Sun mode KB CLK do not connect do not connect KB IN do not connect KB OUT MOUSE DATA do not connect KB DATA do not connect do not connect MOUSE IN MOUSE CLK do not connect A-31 Themis Computer...
  • Page 100 USPIIi-1v Hardware Manual A-32 Themis Computer...

  • Page 101: Bjumper And Solder Bead Configurations

    BJumper and Solder Bead Configurations Overview This appendix provides a summary of the solder beads and jumpers configuration on the USPIIi-1v. Jumpers are considered to be ‘field configurable’ and may be altered by a user on site. Solder beads are considered to be factory configurable.
  • Page 102 Figure B-1 "Baseboard Jumper Locations" on page B-3, provides the location of the various jumpers on the USPIIi-1v baseboard. Note that the number 1 position on the jumper is identified with a square marking for the pin instead of a circle.

  • Page 103: Figure B-1. Baseboard Jumper Locations

    JP3302 JP3303 JP4902 J1501 JP3301 JP1401 JP1601 JP3801 JP4902 JP3301 JP3302 JP3303 JP3304 JP4901 JP4201 JP3901 JP1502 USPIIi-1V - DEFAULT JUMPERS INSTALLED JP1401 JP1601 JP3801 JP3901 All other jumpers are removed by DEFAULT Figure B-1. Baseboard Jumper Locations Themis Computer...

  • Page 104: I/O Board Jumpers

    Figure B-2 "I/O Board Jumper Locations" on page B-5, provides the location of the various jumpers on the USPIIi-1v baseboard. Note that the number 1 position on the jumper is identified with a square marking for the pin instead of a circle.

  • Page 105: Figure B-2. I/O Board Jumper Locations

    B. Jumper and Solder Bead Configurations Figure B-2. I/O Board Jumper Locations Themis Computer...

  • Page 106: Pmc Carrier Board Jumpers

    USPIIi-1v Hardware Manual B.2.3 PMC Carrier Board Jumpers There are no jumpers on the PMC Carrier Board. Factory Configurables B.3.1 Baseboard Solder Beads Table B-3. Baseboard Component Side Solder Beads Solder Bead Setting Description SB3202 Open (Default) Chassis GND RF is coupled to GND for noise reduction...
  • Page 107 +12 V to FLASH SB3501, 3502 Used by Themis Computer for programming and testing of EPLD. Figure B-3 "Baseboard Component Side Solder Bead Locations" on page B-8 and Figure B-4 "Baseboard Solder Side Solder Bead Locations" on page B-9 provide the location of the baseboard solder beads.

  • Page 108: Figure B-3. Baseboard Component Side Solder Bead Locations

    USPIIi-1v Hardware Manual SB3302 SB2401 SB3202 Figure B-3. Baseboard Component Side Solder Bead Locations Themis Computer...

  • Page 109: Figure B-4. Baseboard Solder Side Solder Bead Locations

    B. Jumper and Solder Bead Configurations SB3501 SB3502 SB1811 SB1809 SB1801 SB1808 SB3305 SB3303 SB3301 SB3304 SB1401 SB3203 Figure B-4. Baseboard Solder Side Solder Bead Locations Themis Computer...

  • Page 110: I/O Board Solder Beads

    USPIIi-1v Hardware Manual B.3.2 I/O Board Solder Beads Table B-5. I/O Board Solder Side Solder Beads Solder Bead Setting Description SB0301-0306 Serial Port C signals on P2 (Default) Serial Port D signals on P2 SB0101 Factory set (Default) Factory set...

  • Page 111: Cfront Panel Diagrams

    CFront Panel Diagrams Introduction The following sections present diagrams of the front panels for all possible configurations of the USPIIi-1v. It is intended as a quick reference for the front panel user I/O on the product. Themis Computer...

  • Page 112: Baseboard Front Panel

    USPIIi-1v Hardware Manual Baseboard Front Panel CONSOLE (TTYA) PS/2 KEYBOARD / MOUSE SCSI PORT A SCSI PORT B ALARM POWER_OK_LED READY SYSTEM_OK_LED PUSH BUTTON RESET RESET Figure C-1. Single Slot Front Panel Themis Computer...

  • Page 113: Baseboard, I/O Board, And Creator Graphics Front Panels

    SCSI PORT B ALARM ALARM POWER_OK_LED POWER_OK_LED SYSTEM_OK_LED READY SYSTEM_OK_LED READY PUSH BUTTON RESET PUSH BUTTON RESET RESET RESET Serial port C or CONSOLE Serial port D or TTYB LINE OUT LINE IN Figure C-2. Double Slot Front Panels Themis Computer...

  • Page 114: Figure C-3. Triple Slot Front Panel

    USPIIi-1v Hardware Manual Baseboard, I/O Board, and PMC Carrier Board Front Panel SUN KB/MS or CONSOLE PS/2 KEYBOARD / MOUSE SCSI PORT A SCSI PORT B ALARM POWER_OK_LED SYSTEM_OK_LED READY PUSH BUTTON RESET RESET Serial port C or CONSOLE Serial port D or TTYB...

  • Page 115: Dboard Diagrams

    DBoard Diagrams Baseboard Board Diagrams Themis Computer...

  • Page 116: Figure D-1. Baseboard Front Panel Diagram

    USPIIi-1v Hardware Manual Ethernet A RJ45-TPE Connector Keyboard/Mouse Connector (Upper, from PCB) Serial Port A Connector (Lower, from PCB) SCSI B (Upper, from PCB) SCSI A (Lower, from PCB Power OK LED System OK LED Push-Button Reset Figure D-1. Baseboard Front Panel Diagram...

  • Page 117: Figure D-2. Baseboard Component Diagram

    3.3V DC-DC Voltage SME2411: Convertor Advance SME 1040 PCI Bridge UltraSPARC-IIi Power Trends PT6503A: SME STP2210: 2.5V DC-DC Reset, Voltage Interrupt, and Convertor Clock IBM043641AULAA or IBM 04181AULA: Hitachi HM67S36130BP Address Cache Data Cache Figure D-2. Baseboard Component Diagram Themis Computer...

  • Page 118: Figure D-3. Baseboard Connector Diagram

    USPIIi-1v Hardware Manual Creator Graphics, PMC Carrier Board UPA Connector Memory Card Connectors Expanded I/O Connector Figure D-3. Baseboard Connector Diagram Themis Computer...

  • Page 119: I/O Board Diagrams

    D. Board Diagrams I/O Board Diagrams VME P2 Siemens Connector Parallel 82532: UART TTY C (Upper Connector) STP2003: TTY D CHEERIO (Lower Connector) Ethernet B Crystal CS4231AKQ: CODEC Line-Out Line-in Figure D-4. I/O Board Component Side Themis Computer...

  • Page 120: Pmc Board

    USPIIi-1v Hardware Manual PMC Board User I/O Adapter Connectors Digital 21150 Bridge Figure D-5. PMC Carrier Board Component Side Themis Computer...

  • Page 121: Figure D-6. Pmc Board Connector Diagram

    D. Board Diagrams PMC #3 Connectors PMC #2 Connectors User I/O Adapter Board Connectors PMC #2 User I/O Connector PMC #1 Connectors Digital 21150 Bridge PMC #1 User I/O Connector Figure D-6. PMC Board Connector Diagram Themis Computer...

  • Page 122: Figure D-7. Paddle Board Component Side

    USPIIi-1v Hardware Manual Paddle Board VME P2 SCSI A (Miniature DB68) AMP: 757844-2 MII Ethernet (Miniature DB40) AMP: 787082-7 Serial Port B (DB-9) AMP 787170-4 Figure D-7. Paddle Board Component Side Themis Computer...

  • Page 123: Eglossary

    Firmware: This is software which stays with the hardware usually in a PROM or similar device. Referred to as OBP in IEEE 1275 standards. In the USPIIi-1v implementation, release version 3.10.x and later are supported. This version comes with the motherboard. The user may upgrade the OBP to a newer version if needed.
  • Page 124 USPIIi-1v Hardware Manual Hardware: On the USPIIi-1v, CPU module, cables, peripheral devices are typical examples of hardware. may: A keyword indicating flexibility of choice with no implied preference. LED: Light-Emitting Diode MII: Medium Independent Interface MMU: Memory Management Unit. NC or N/C: Not Connected.
  • Page 125 VME: Versa Module Europe. VME is a standard for chassis (rack) based industrial computer systems based on 32- or 64- bit system architectures. Write Cycle: A VMEbus cycle used to transfer 1, 2, 3, 4 or 8 bytes from a Master to a Slave. Themis Computer...
  • Page 126 USPIIi-1v Hardware Manual Themis Computer...
  • Page 127 Place Stamp Here Themis Computer 3185 Laurelview Court Fremont, CA 94538 Attn: Publications Department...
  • Page 128 Reader Comment Card We welcome your comments and suggestions to help improve the USPIIi-1V User’s Manual. Please take time to let us know what you think about these manuals. • The information provided in the manuals was complete. Agree___ Disagree___ Not Applicable___ •...

Table of Contents