Schematic Sheet #6; Clear Circuit; Read Back; Monitor Drive Signals - Lear Siegler ADM-3 Maintenance Manual

6.6 SCHEMATIC SHEET #6 -
CLEAR CIRCUIT
READ BACK
MONITOR DRIVE SIGNALS
CURSOR GENERATION
6.6.1 CLEAR Circuit
The 74123 (retriggerable one-shot, Dl,) located
in zone D4 provides the power on clear signal.
The RC circuit is connected to the positive
trigger input. Therefore, when the power is up
and the capacitor finally charges to the input
threshold, the one-shot triggers off and creates
the reset signal. This unit is unusual in that
every single storage element in the system is
reset with the CLEAR pulse except for the re-
fresh memories. This was done to accommodate
the automatic board testers. The signal labeled
TESTER INITIALIZE, entering the circuit at
D4-1 (7400, zone C3) accomplishes the same
function as the power on clear except that the
signal is generated by the automatic tester.
These two clearing sources are combined at
D4-3 (7400, zone C3) and is called CLEAR. A
positive level at this point is the clearing level.
This signal is buffered through six inverters to
create the negative-going CLEAR signal. Each
inverter has only 10 loads and they were usedJ
instead of a power buffer because of automatic
board tester restrictions.
6.6.2 READ BACK
The flip-flop located in zone C3 (B5-6, 74S113)
is part ofthe READ BACK feature. This flop can
set only if pin 22 on the main
110 connector Jl is
held to ground. READ BACK is a test only
feature therefore only internal test cables
should have this pin grounded. This function is
initiated by issuing an USASCII BEL code
(octal 007) through the normal data input which
sets this flip-flop. The ADM-3 then responds by
sert.ding all data on the top line of the display
6-16
from the cursor position to the end of the line
inclusive. The screen is rolled one line but the
data remains on the screen and the bottom line
is not erased. The cursor remains on the last
character position transmitted which is the last
position on the line. The READ flip-flop is
cleared at the end of the operation when the
CURSOR register overflows.
6.6.3 MONITOR DRIVE Signals
The monitor drive signals, HDRIVE and
VDRIVE are generated in zones Cl and Dl. The
horizontal drive signal, HDRIVE never moves
regardless of the position of the 50/60 Hz selec-
tion switch. However, the VDRIVE signal
changes between 50 Hz and 60 Hz refresh in
order to maintain the same relative position of
the video display on the display screen. (See the
MAIN TIMING DIAGRAM for the positioning
of these drive signals.
6.6.4 CURSOR Generation
The circuit at the bottom of this schematic
generates the cursor position for the video
presentation on the display screen. It uses only
two 7485 comparators because the cursor can
only reside on one line of the display. It essen-
tially compares the CURSOR register (WC)
against the dynamic value of the CURSOR
POSITION counters (CC). This comparison is
really two character times before the actual
display times since the system counters are
always two character times earlier. Therefore,
the two flip-flops (BI2-5 and BI2-9, zone AI)
delay the compared output by two character
times before the video cursor is generated. The
flop BII-6 (7474, zone A3) labeled CUR STOP
and gate BI0-8 (7408, zone A3) combine to
position the cursor display on .the proper two
raster lines. This occurs below the bottom line
of the screen.