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2. WAVEFORMS & TIMING OF MAIN SIGNAL LINES
2.1 Processor
2.1.1 Audio system
Note: Switch to Digital Input mode by connecting the optical cable
to DIGITAL IN 1 or 2, and pressing the INPUT key.
Switch to Analog Input mode by connecting the audio cable
to LINE IN, and pressing the INPUT key.
• Master clock
MCK (IC12-104pin) : 12.288 MHz (fixed)
MCKADDA (IC5-6pin) : 12.288 MHz (fixed) when in analog
input mode;
When in Digital Input mode, 12.288 MHz for an input source
sampling frequency of 48 kHz.
11.298 MHz for an input sampling frequency of 44.1 kHz; 8.192
MHz for an input sampling frequency of 32 kHz
• DIR-DECODER period
Check LRCK (IC11-12pin), BCK (IC 11-14pin), INDATA (IC11-
10pin).
At power-ON, and in Digital Input mode, any playback source is
okay.
Monitor view is shown in Fig. 1 and detailed timing is shown in
Fig. 2.
Lch
Rch
LRCK
BCK
INDATA
Note 1: Example shows 44.1 kHz for LRCK; 48 kHz and
32 kHz are also used.
LRCK
BCK
INDATA
1 bit offset (I
2
S format)
• ACD-DECODER period
Check LRCK (IC11-12pin), BCK(IC 11-14pin), INDATA (IC11-
10pin).
At power-ON, and in Digital Input mode, any playback source is
okay.
Monitor view is shown in Fig. 3 and detailed timing is shown in
Fig. 4.
LRCK
BCK
INDATA
Note 2: LRCK is fixed at 48 kHz.
LRCK
BCK
INDATA
2
1 bit offset (I
S format)
Fig1
16 bit
Fig 2
Lch
Rch
Fig 3
24 bit
Fig 4
• DECODER-MAIN DSP period
Check LRCK (IC11-12pin), BCK (IC 11-14pin), FLRSG (IC11-4pin),
SLRSG (IC11-5pin), CLFSG (IC11-6pin), OTHSG (IC11-7pin).
The playback source at power-ON, and Digital Input mode is Dolby
Digital or DTS, or a 5.1ch source for MPEG-AAC.
The view on the monitor when OFF or VIRTUAL FRONT is se-
lected with the OUTPUT key is shown in Fig. 5. The detailed timing
is shown in Fig. 6.
LRCK
BCK
FLRSG
SLRSG
CLFSG
Note 3: Example shows 48 kHz for LRCK, but 44.1 kHz and
32 kHz may also be used.
LRCK
BCK
FLRSG
SLRSG
CLFSG
2
1 bit offset (I
S format)
Fig. 7 shows the monitor view when VIRTUAL 5.1 is selected with
the OUTPUT key. (Detailed timing is the same as in Fig. 6.)
Fig. 8 shows the monitor view when VIRTUAL 6.1 is selected with
the OUTPUT key. (Detailed timing is the same as in Fig. 6.)
LRCK
BCK
FLRSG
SLRSG
CLFSG
Note 3: Example shows 48 kHz for LRCK, 44.1 kHz and
32 kHz are also used.
LRCK
BCK
FLRSG
SLRSG
CLFSG
OTHSG
Note 3: Example shows 48 kHz for LRCK, 44.1 kHz and
32 kHz are also used.
• MAIN DSP-DAC period
Check LRCK (IC5-5pin), BCK (IC5-4pin), VPOUT2 (IC15-3pin).
At power-ON, and Digital Input mode or Analog Input mode, any
playback source is okay.
A monitor view is shown in Fig. 9 and the detailed timing is shown
in Fig. 10.
DP-IF8000
FLch
FRch
LFE
Fig 5
Fig 6
FL
FR
SL
SR
C
LFE
Fig 7
FL
FR
SL
SR
C
LFE
CS
Fig 8
5
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