Chassis Plans MX8 Technical Reference

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MX8

S6240-xxx

TECHNICAL REFERENCE

Intel

Pentium

Intel

Celeron

PROCESSOR-BASED

SBC

Table of Contents

Summary of Contents for Chassis Plans MX8

Page 1 S6240-xxx TECHNICAL REFERENCE ® ® Intel Pentium ® ® Intel Celeron PROCESSOR-BASED...
Page 3 In no event shall Chassis Plans be liable for any defect in hardware or software or loss or inadequacy of data of any kind, or for any direct, indirect, incidental or consequential damages arising out of or in connection with the performance or use of the product or information provided.
Page 4 This manual is as complete and factual as possible at the time of printing; however, the IABILITY information in this manual may have been updated since that time. Chassis Plans ISCLAIMER reserves the right to change the functions, features or specifications of their products at any time, without notice.
Page 5: Table Of Contents
MX8 Technical Reference Table of Contents Specifications ..........1-1 Introduction .
Page 6 MX8 Technical Reference Table of Contents Specifications (continued) Power Fail Detection ........1-11 Battery .
Page 7 MX8 Technical Reference Table of Contents Advanced Setup..........4-1 CPU Configuration.
Page 9 MX8 Technical Reference _______________________________________________________________________ ANDLING RECAUTIONS WARNING: This product has components which may be damaged by electrostatic discharge. _______________________________________________________________________ To protect your single board computer (SBC) from electrostatic damage, be sure to observe the following precautions when handling or storing the board: •...
Page 11: Before You Begin
ECC (72-bit) or non-ECC (64-bit) DDR memory • Unbuffered configuration The MX8 supports bootup from a LAN device. If you are not booting from a LAN OOT FROM device, the boot from LAN options on the Boot Device Priority screen should always be set to Disabled to eliminate unnecessary delays during the bootup process.
Page 12 Before You Begin MX8 Technical Reference The MX8 also requires that +3.3V must be applied to the backplane from the power ® supply, as specified in the PCI Industrial Computer Manufacturers Group (PICMG ) 1.0 Specification. When using a backplane which is not a Chassis Plans product, check with your backplane manufacturer to ensure that the backplane provides +3.3V to the SBC.
Page 13: Specifications
PCI/ISA and PCI-X backplanes and provide full PC compatibility for the system expansion slots. The MX8-NS models have all of the standard features of the MX8, except they do not include the Adaptec SCSI controller or the Ultra160 SCSI port.
Page 14: Features
Specifications MX8 Technical Reference ODELS Model # Model Name Speed CONTINUED “No SCSI” Models (continued): ® ® Intel Celeron Processor - 400MHz FSB/128K cache: S6240-827-xM MX8/2.5C-NS 2.5GHz S6240-826-xM MX8/2.4C-NS 2.4GHz S6240-825-xM MX8/2.3C-NS 2.3GHz S6240-824-xM MX8/2.2C-NS 2.2GHz S6240-823-xM MX8/2.1C-NS 2.1GHz S6240-822-xM MX8/2.0C-NS...
Page 15 MX8 Technical Reference Specifications • Watchdog timer EATURES CONTINUED • System hardware monitor • Full PC compatibility Chassis Plans...
Page 16: Sbc Block Diagram
Specifications MX8 Technical Reference SBC B LOCK IAGRAM Chassis Plans...
Page 17: Sbc Board Layout
MX8 Technical Reference Specifications SBC B OARD AYOUT Chassis Plans...
Page 18: Processor
Specifications MX8 Technical Reference ® ® • Intel Pentium 4 microprocessor ROCESSOR • 3.2GHz, 3.0GHz or 2.8GHz with 1M cache and a 800MHz Front Side Bus (FSB) • 3.06GHz, 2.8GHz, 2.66GHz, 2.53GHz or 2.4GHz with 512K cache and a 533MHz FSB ®...
Page 19: Netburst Micro-Architecture
MX8 Technical Reference Specifications All processors include a 12K level 1 (L1) Execution Trace Cache. Processors which have 1M of L2 cache memory have a 16K data cache; all other processors have an 8K data cache. ™ NetBurst micro-architecture defines the techniques Intel uses to enhance the processor’s URST execution of the BIOS, operating system and application software.
Page 20: Error Checking And Correction
Specifications MX8 Technical Reference The following DIMM sizes are supported: DIMM Size DIMM Type 64MB Unbuffered 8M x 72 128MB Unbuffered 16M x 72 256MB Unbuffered 32M x 72 512MB Unbuffered 64M x 72 Unbuffered 128M x 72 The memory interface supports ECC modes via BIOS setting for multiple-bit error...
Page 21: Pci Ethernet Interfaces (Dual)
MX8 Technical Reference Specifications The System Hardware Monitor connector (P18) provides an external interface for user functionality. Pin assignments for this connector are as follows: Pin #/Definition Description Pin 1 - GND System Ground Pin 2 - GPO General Purpose Output Active low open drain output.
Page 22: Hub Interface
Ultra160 SCSI adapter. You may press <Ctrl> + <A> to invoke the configuration utility. ATA/150 The primary and secondary Serial ATA (SATA) ports on the MX8 comply with the SATA ERIAL 1.0 specification and support two independent SATA storage devices such as hard disks ORTS and CD-RW devices.
Page 23: Ps/2 Mouse Interface
MX8 Technical Reference Specifications PS/2 M The SBC is compatible with a PS/2-type mouse. The mouse connection can be made by OUSE using either the PS/2 mouse header or the bracket mounted mouse/keyboard mini DIN NTERFACE connector. The mouse may be connected directly to the mini DIN connector or to the "mouse"...
Page 24: Power Requirements
+12V from an external power supply that conforms to the ATX12V power specification. The external power supply must have a wattage rating of 250W or higher. The MX8 also requires that +3.3V must be applied to the backplane from the power ®...
Page 25: Configuration Jumpers
MX8 Technical Reference Specifications The setup of the configuration jumpers on the SBC is described below. * indicates the ONFIGURATION default value of each jumper. UMPERS ______________________________________________________________________ NOTE: For two-position jumpers (3-post), "TOP" is toward the memory sockets; "BOTTOM" is toward the edge fingers.
Page 26: Ethernet Leds And Connectors
Specifications MX8 Technical Reference ONFIGURATION UMPERS Jumper Description CONTINUED JU10/JU11 System Flash ROM Operational Modes The Flash ROM has two programmable sections: the Boot Block for “flashing” in the BIOS and the Main Block for the executable BIOS and PnP parameters. Normally only the Main Block is updated when a new BIOS is flashed into the system.
Page 27: System Bios Setup Utility
MX8 Technical Reference Specifications THERNET ONNECTORS LED/Connector Description CONTINUED Link/Speed LED Bi-color (green/orange) LED which identifies the link status and connection speed. This is the lower LED on the LAN connector (i.e., toward the edge connectors). Green Indicates a valid link at either 1000-Mb/s or 10-Mb/s, depending on the setting of the associated Speed LED jumper (JU5 or JU7).
Page 28: Connectors
Specifications MX8 Technical Reference ______________________________________________________________________ ONNECTORS NOTE: Pin 1 on the connectors is indicated by the square pad on the PCB. ______________________________________________________________________ 10/100/1000Base-T Ethernet Connector - LAN 2 8 pin shielded RJ-45 connector, Belfuse #0826-1X1T-23 Signal TRP1+ TRP1- TRP2+ TRP3+...
Page 29 MX8 Technical Reference Specifications ONNECTORS CONTINUED Speaker Port Connector 4 pin single row header, Amp #640456-4 Signal Speaker Data Serial Port 1 Connector 10 pin dual row header, Amp #103308-1 Signal Signal Carrier Detect Data Set Ready-I Receive Data-I Request to Send-O...
Page 30 Specifications MX8 Technical Reference ONNECTORS CONTINUED PS/2 Mouse and Keyboard Connector 6 pin mini DIN, Kycon #KMDG-6S-B4T Signal Ms Data Kbd Data Power (+5V fused) with self-resetting fuse Ms Clock Kbd Clock P9A - PS/2 Mouse Header 6 pin single row header, Amp #640456-6...
Page 31 MX8 Technical Reference Specifications ONNECTORS CONTINUED P11 - Primary IDE Hard Drive Connector (continued) Signal Signal IRQ 14 Add 1 PCBL DET * Add 0 Add 2 CS 1P CS 3P IDEACTP P11A - Secondary IDE Hard Drive Connector 40 pin dual row header, 3M #30340-6002HB...
Page 32 Specifications MX8 Technical Reference ONNECTORS CONTINUED P13 - Ultra160 SCSI Connector 68 pin high density connector, Amp #749069-7 Signal Signal SCD12 SCD#12 SCD13 SCD#13 SCD14 SCD#14 SCD15 SCD#15 SCDPH SCDPH# SCD0 SCD#0 SCD1 SCD#1 SCD2 SCD#2 SCD3 SCD#3 SCD4 SCD#4...
Page 33 MX8 Technical Reference Specifications ONNECTORS CONTINUED P15 - Video Interface Connector 15 pin connector, Amp #1-1470250-3 Pin Signal Pin Signal Signal 1 Red 2 Green EEDI 3 Blue HSYNC 4 NC VSYNC 5 Gnd EECS P16 - 10/100/1000Base-T Ethernet Connector - LAN 1...
Page 34 Specifications MX8 Technical Reference ONNECTORS CONTINUED P19 - CPU Fan 3 pin single row header, Molex #22-23-2031 Signal +12V FanTach P21 - Power Good LED 2 pin single row header, Amp #640456-2 Signal LED - LED + P22 - System Management Bus Connector...
Page 35 MX8 Technical Reference Specifications ONNECTORS CONTINUED P28 - SATA Port 2 7 pin vertical connector, Molex #67491-0031 Signal Chassis Plans 1-23...
Page 37: Isa/Pci Reference
MX8 Technical Reference ISA/PCI Reference Chapter 2 ISA/PCI Reference ISA B UMBERING 62-pin ISA Bus Connector Component Side of Board 36-pin ISA Bus Connector Chassis Plans...
Page 38: Isa Bus Pin Assignments
ISA/PCI Reference MX8 Technical Reference ISA B The following tables summarize pin assignments for the Industry Standard Architecture (ISA) Bus connectors. SSIGNMENTS I/O Pin Signal Name I/O Pin Signal Name IOCHK# Ground RESDRV Power IRQ9 Power DRQ2 -12V Power NOWS#...
Page 39: Isa Bus Signal Descriptions
MX8 Technical Reference ISA/PCI Reference ISA B The following is a description of the ISA Bus signals. All signal lines are TTL- IGNAL compatible. ESCRIPTIONS AEN (O) Address Enable (AEN) is used to degate the microprocessor and other devices from the I/O channel to allow DMA transfers to take place.
Page 40 ISA/PCI Reference MX8 Technical Reference IO16# (I) I/O 16-bit Chip Select (IO16#) signals the system board that the present data transfer is a 16-bit, 1 wait-state, I/O cycle. It is derived from an address decode. IO16# is active low and should be driven with an open collector or tri-state driver capable of sinking 20 mAmps.
Page 41 MX8 Technical Reference ISA/PCI Reference NOWS# (I) The No Wait State (NOWS#) signal tells the microprocessor that it can complete the present bus cycle without inserting any additional wait cycles. In order to run a memory cycle to a 16-bit device without wait cycles, NOWS# is derived from an address decode gated with a Read or Write command.
Page 42 ISA/PCI Reference MX8 Technical Reference T-C (O) Terminal Count (T-C) provides a pulse when the terminal count for any DMA channel is reached. Chassis Plans...
Page 43: I/O Address Map
MX8 Technical Reference ISA/PCI Reference I/O A DDRESS Hex Range Device 000-01F DMA Controller 1 020-03F Interrupt Controller 1, Master 040-05F Timer 060-06F 8042 (Keyboard) 070-07F Real-time Clock, NMI (non-maskable interrupt) Mask 080-09F DMA Page Register 0A0-0BF Interrupt Controller 2...
Page 44: Pci Local Bus Overview
ISA/PCI Reference MX8 Technical Reference PCI L The PCI (Peripheral Component Interconnect) Local Bus is a high performance, 32-bit or OCAL 64-bit bus with multiplexed address and data lines. It is intended for use as an inter- VERVIEW connect mechanism between highly integrated peripheral controller components, peripheral add-in boards and processor/memory systems.
Page 45: Pci Local Bus Signal Definition
MX8 Technical Reference ISA/PCI Reference PCI L The PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for OCAL a master to handle data and addressing, interface control, arbitration and system IGNAL EFINITION functions. The diagram below shows the pins in functional groups, with required pins on the left side and optional pins on the right side.
Page 46: Pci Local Bus Pin Numbering
ISA/PCI Reference MX8 Technical Reference PCI L OCAL UMBERING Component Side of Board 5-volt/32-bit PCI Connector 2-10 Chassis Plans...
Page 47: Pci Local Bus Pin Assignments
MX8 Technical Reference ISA/PCI Reference PCI L The PCI Local Bus pin assignments shown below are for the PCI option slots on the OCAL backplane. SSIGNMENTS The PCI Local Bus specifies both 5-volt and 3.3-volt signaling environments. The following bus pin assignments are for the 5-volt connector. The 3.3-volt connector bus pin assignments are the same with the following exceptions: The pins noted as +V (I/O) are +5 volts or +3.3 volts, depending on which...
Page 48 ISA/PCI Reference MX8 Technical Reference PCI L OCAL SSIGNMENTS CONTINUED I/O Pin Signal Name I/O Pin Signal Name +3.3V TRDY# DEVSEL# STOP# LOCK# +3.3V PERR# SDONE +3.3V SBO# SERR# +3.3V C/BE1# AD15 AD14 +3.3V AD13 AD12 AD11 AD10 †† Connector Key...
Page 49 MX8 Technical Reference ISA/PCI Reference PCI L The following pin assignments apply only to backplanes with 64-bit PCI option slots. OCAL SSIGNMENTS CONTINUED I/O Pin Signal Name I/O Pin Signal Name Connector Key Connector Key 64-bit spacer Connector Key Connector Key...
Page 50: Pci Local Bus Signal Descriptions
ISA/PCI Reference MX8 Technical Reference PCI L The PCI Local Bus signals are described below and may be categorized into the OCAL following functional groups: IGNAL ESCRIPTIONS • System Pins • Address and Data Pins • Interface Control Pins •...
Page 51 MX8 Technical Reference ISA/PCI Reference C/BE[7::4]# (optional) Bus Command and Byte Enables are multiplexed on the same pins. During an address phase (when using the DAC command and when REQ64# is asserted), the actual bus command is transferred on C/BE[7::4]#; otherwise, these bits are reserved and indeterminate. During a data phase, C/BE[7::4]# are byte enables indicating which byte lanes carry meaningful data when REQ64# and ACK64# are both asserted.
Page 52 ISA/PCI Reference MX8 Technical Reference Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI agents. The master drives PAR for address and write data phases; the target drives PAR for read data phases. PAR64 (optional) Parity Upper DWORD is the even parity bit that protects AD[63::32] and C/BE[7::4]#.
Page 53 MX8 Technical Reference ISA/PCI Reference STOP# Stop indicates that the current target is requesting the master to stop the current transaction. TCK (optional) Test Clock is used to clock state information and test data into and out of the device during operation of the TAP (Test Access Port).
Page 54 ISA/PCI Reference MX8 Technical Reference PICMG E The pin assignments shown below are for the PICMG portion of the edge connector on the processor board. These pin assignments match those of the PICMG connector of the ONNECTOR SSIGNMENTS processor slot on the backplane.
Page 55: Picmg Edge Connector Pin Assignments
MX8 Technical Reference ISA/PCI Reference PICMG E ONNECTOR SSIGNMENTS CONTINUED I/O Pin Signal Name I/O Pin Signal Name Connector Key Connector Key Connector Key Connector Key C/BE0# ACK64# REQ64# 32-bit connector end Chassis Plans 2-19...
Page 56 ISA/PCI Reference MX8 Technical Reference PICMG E The following pin assignments apply only to SBCs with 64-bit PICMG connectors. ONNECTOR SSIGNMENTS CONTINUED I/O Pin Signal Name I/O Pin Signal Name Connector Key Connector Key 64-bit spacer Connector Key Connector Key...
Page 57: System Bios
MX8 Technical Reference System BIOS Chapter 3 System BIOS BIOS O Sections 3 through 7 of this manual describe the operation of the American Megatrends PERATION AMIBIOS and the BIOS Setup Utility. Refer to Running AMIBIOS Setup later in this chapter for standard Setup screens, options and defaults.
Page 58: Password Entry
System BIOS MX8 Technical Reference Normally, the only POST routine visible on the screen is the memory test. The following screen displays when the system is powered on: AMIBIOS (C)2002 American Megatrends, Inc. TRENTON Technology Inc. Press DEL to run Setup...
Page 59 MX8 Technical Reference System BIOS Enter CURRENT Password: Type the password and press <Enter>. _______________________________________________________________________ NOTE: The null password is the system default and is in effect if a password has not been assigned or if the CMOS has been corrupted. In this case, the password prompt does not display.
Page 60: Bios Errors
System BIOS MX8 Technical Reference BIOS Errors If an error is encountered during the diagnostic checks performed when the system is powered on, the error is reported in one of two different ways: 1) If the error occurs before the display device is initialized, a series of beeps is transmitted.
Page 61: Running Amibios Setup
MX8 Technical Reference System BIOS AMIBIOS Setup keeps a record of system parameters, such as date and time, disk drives UNNING AMIBIOS S and other user-defined parameters. The Setup parameters reside in the Read Only ETUP Memory Basic Input/Output System (ROM BIOS) so that they are available each time the system is turned on.
Page 62: Bios Setup Utility Main Menu
System BIOS MX8 Technical Reference BIOS S When you press <F1> in response to an error message received during the POST ETUP routines or when you press the <Del> key to enter the BIOS Setup Utility, the following TILITY screen displays:...
Page 63: Bios Setup Utility Options
MX8 Technical Reference System BIOS If you enter an invalid value in any field, the screen will revert to the previous value when you move to the next field. When you change the value for the month, day or year field, the day of the week changes automatically when you move to the next field.
Page 64 System BIOS MX8 Technical Reference • Hard Disk Write Protect • IDE Detect Time Out (Sec) • ATA(PI) 80Pin Cable Detection • Floppy Configuration • Floppy A/Floppy B • SuperIO Configuration • OnBoard Floppy Controller • Serial Port1 Address/Serial Port2 Address •...
Page 65: Change Supervisor Password
MX8 Technical Reference System BIOS • Onboard Adaptec SCSI • Onboard ATI Radeon Video • IRQs 3, 4, 5, 7, 9, 10, 11, 14 and 15 • DMA Channels 0, 1, 3 5, 6 and 7 • Reserved Memory Size •...
Page 66 System BIOS MX8 Technical Reference • Select Chipset to make changes to Chipset Setup parameters as described in the Chipset Setup chapter of this manual. The following options may be modified: • NorthBridge Configuration • DRAM Frequency • Configure DRAM Timing by SPD •...
Page 67 MX8 Technical Reference System BIOS When you select Security from the BIOS Setup Utility Main Menu, the following Setup ECURITY ETUP screen displays: BIOS SETUP UTILITY Main Advanced PCIPnP Boot |Security| Chipset Exit Security Settings Install or Change the _____________________________________________ password.
Page 68 System BIOS MX8 Technical Reference The Change Supervisor Password feature can be configured so that a password must be entered each time the system boots or just when a user attempts to enter the BIOS Setup Utility. _______________________________________________________________________ NOTE: The null password is the system default and is in effect if a password has not been assigned or if the CMOS has been corrupted.
Page 69 MX8 Technical Reference System BIOS Press the <Enter> key to return to the Security screen. Installed displays on the screen next to the Supervisor Password option, indicating the password has been accepted. This setting will remain in effect until the supervisor password is either disabled or discarded upon exiting the BIOS Setup Utility.
Page 70: Disabling Supervisor Password
System BIOS MX8 Technical Reference Two options are available: • Select Setup to have the password prompt appear only when an attempt is made to enter the BIOS Setup Utility program. • Select Always to have the password prompt appear each time the system is powered on.
Page 71: Boot Sector Virus Protection
MX8 Technical Reference System BIOS The Setup screen displays the system option: Boot Sector Virus Protection [Disabled] Available options are: Disabled Enabled _______________________________________________________________________ NOTE: You should not enable boot sector virus protection when formatting a hard drive. _______________________________________________________________________ Chassis Plans...
Page 72 System BIOS MX8 Technical Reference This page intentionally left blank. 3-16 Chassis Plans...
Page 73: Exit Menu
MX8 Technical Reference System BIOS When you select Exit from the BIOS Setup Utility Main Menu, the following screen displays: BIOS SETUP UTILITY Main Advanced PCIPnP Boot Security Chipset |Exit| Exit Options Exit system setup _____________________________________________ after saving the changes.
Page 74 System BIOS MX8 Technical Reference You have two options: • Select Ok to save the system parameters and continue with the booting process. • Select Cancel to return to the BIOS Setup Utility screen. Discard Changes and Exit When the Discard Changes and Exit option is selected, the BIOS Setup Utility exits without saving the changes in the CMOS.
Page 75 MX8 Technical Reference System BIOS Load Optimal or Failsafe Defaults Each AMIBIOS Setup option has two default settings (Optimal and Failsafe). These settings can be applied to all AMIBIOS Setup options when you select the appropriate configuration option from the BIOS Setup Utility Main Menu.
Page 76 System BIOS MX8 Technical Reference You have two options: • Select Ok to load the Failsafe default settings. • Select Cancel to leave the current values in effect. Copyright 2004 by Trenton Technology Inc. All rights reserved. 3-20 Chassis Plans...
Page 77: Advanced Setup
MX8 Technical Reference Advanced Setup Chapter 4 Advanced Setup When you select Advanced from the BIOS Setup Utility Main Menu, the following DVANCED ETUP Setup screen displays: BIOS SETUP UTILITY Main |Advanced| PCIPnP Boot Security Chipset Exit Advanced Settings Configure CPU.
Page 78: Cpu Configuration
Advanced Setup MX8 Technical Reference CPU Configuration The CPU Configuration subscreen provides you with information about the processor in your system. The following option is displayed: • Max CPUID Value Limit • Hyper Threading Technology IDE Configuration The options on the IDE Configuration subscreens allow you to set up or modify param- eters for your IDE controller and hard disk drive(s).
Page 79 MX8 Technical Reference Advanced Setup SuperIO Configuration The options on the SuperIO Configuration subscreen allow you to set up or modify parameters for your on-board peripherals. The following options may be modified: • OnBoard Floppy Controller • Serial Port1 Address/Serial Port2 Address •...
Page 80 Advanced Setup MX8 Technical Reference This page intentionally left blank. Chassis Plans...
Page 81 MX8 Technical Reference Advanced Setup When you select CPU Configuration from the Advanced Setup Screen, the following Setup screen displays: ONFIGURATION ETUP BIOS SETUP UTILITY |Advanced| Configure advanced CPU settings This should be enabled in order to boot legacy Manufacturer: Intel OSes that cannot Brand String: Intel(R) Pentium(R) 4 CPU 3.20GHz...
Page 82 Advanced Setup MX8 Technical Reference Hyper Threading Hyper-Threading is a feature which can be used to maximize the processor’s efficiency and execution speed by using the single processor as two logical processors. The two logical processors have separate architectural and local APIC states, but unlike separate physical processors, these logical processors share common execution resources.
Page 83: Ide Configuration
MX8 Technical Reference Advanced Setup When you select IDE Configuration from the Advanced Setup Menu, a Setup screen similar to the following displays: ONFIGURATION BIOS SETUP UTILITY |Advanced| IDE Configuration ________________________________________________ IDE Configuration [P-ATA Only] S-ATA Running Enhanced Mode [Yes]...
Page 84 Advanced Setup MX8 Technical Reference Four options are available: • Select Disabled to disable all IDE ports. • Select P-ATA Only to allow up to six devices, four parallel and two serial. The number of devices available depends on the setting of the S-ATA Running Enhanced Mode option described below.
Page 85 MX8 Technical Reference Advanced Setup Combined Mode Option This option allows you to specify the configuration of the parallel and serial devices when the IDE Configuration option is set to P-ATA & S-ATA. A total of two parallel and two serial ATA devices will be available as described below.
Page 86 Advanced Setup MX8 Technical Reference Configure S-ATA as RAID If the S-ATA Running Enhanced Mode option is set to No, this option is not available. The Setup screen displays the system option: Configure S-ATA as RAID [No] Available options are:...
Page 87 MX8 Technical Reference Advanced Setup IDE Detect Time Out (Sec) This option allows you to select the time-out value (in seconds) for detecting an ATA/ ATAPI device. The Setup screen displays the system option: IDE Detect Time Out (Sec) [35]...
Page 88 Advanced Setup MX8 Technical Reference This page intentionally left blank. 4-12 Chassis Plans...
Page 89: Ide Device Setup
MX8 Technical Reference Advanced Setup IDE D When you select one of the IDE devices from the IDE Configuration screen, a Setup EVICE ETUP screen similar to the following displays: BIOS SETUP UTILITY |Advanced| Primary IDE Master Select the type...
Page 90 Advanced Setup MX8 Technical Reference Available options are: Not Installed Auto CDROM ARMD If Not Installed is selected, the other options on the bottom portion of this screen do not display. LBA/Large Mode This option allows you to enable IDE LBA (Logical Block Addressing) Mode for the specified IDE drive.
Page 91 MX8 Technical Reference Advanced Setup PIO Mode IDE Programmed I/O (PIO) Mode programs timing cycles between the IDE drive and the programmable IDE controller. As the PIO mode increases, the cycle time decreases. Set the PIO Mode option to Auto to have AMIBIOS select the PIO mode used by the IDE drive being configured.
Page 92 Advanced Setup MX8 Technical Reference The Setup screen displays the system option: S.M.A.R.T. [Auto] Available options are: Auto Disabled Enabled 32Bit Data Transfer If the 32Bit Data Transfer parameter is set to Enabled, AMIBIOS enables 32-bit data transfers. If the host controller does not support 32-bit transfer, this feature must be set to Disabled.
Page 93: Floppy Configuration
MX8 Technical Reference Advanced Setup When you select Floppy Configuration from the Advanced Setup Menu, the following LOPPY Setup screen displays: ONFIGURATION BIOS SETUP UTILITY |Advanced| Floppy Configuration Select the type of _____________________________________________ floppy drive connected to the Floppy A [1.44 MB 3½]...
Page 94 Advanced Setup MX8 Technical Reference Available options are: Disabled 360 KB 5¼" 1.2 MB 5¼" 720 KB 3½" 1.44MB 3½" 2.88MB 3½" 4-18 Chassis Plans...
Page 95: Superio Configuration
MX8 Technical Reference Advanced Setup When you select SuperIO Configuration from the Advanced Setup Menu, the UPER following Setup screen displays: ONFIGURATION SuperIO Chipset Smc27X |Advanced| Configure Smc27X Super IO Chipset Allows BIOS to enable _______________________________________________ or disable floppy controller.
Page 96 Advanced Setup MX8 Technical Reference Serial Port1 Address/Serial Port2 Address Each of these options enables the specified serial port on the SBC and establishes the base I/O address and the number of the interrupt request for the port. The Setup screen displays the system option:...
Page 97 MX8 Technical Reference Advanced Setup Available options are: Disabled When AMIBIOS checks for parallel ports, any off-board parallel ports found are left at their assigned addresses. The on-board Parallel Port is automatically configured with the first available address not used by an off-board parallel port.
Page 98 Advanced Setup MX8 Technical Reference Available options are: IRQ5 IRQ7 4-22 Chassis Plans...
Page 99: Remote Access Configuration
MX8 Technical Reference Advanced Setup When you select Remote Access Configuration from the Advanced Setup Menu, the EMOTE CCESS following Setup screen displays: ONFIGURATION BIOS SETUP UTILITY |Advanced| Configure Remote Access Type and Parameters Select Remote access _____________________________________________ type Remote Access...
Page 100 Advanced Setup MX8 Technical Reference Available options are: Disabled Serial Serial Port Number This option specifies the serial port on which remote access is to be enabled. If the Remote Access option is set to Disabled, this option is not available.
Page 101: Usb Configuration
MX8 Technical Reference Advanced Setup When you select USB Configuration from the Advanced Setup Menu, the following Setup screen displays: ONFIGURATION BIOS SETUP UTILITY |Advanced| USB Configuration Enables USB host ___________________________________________ controllers. Module Version - 2.23.0-7.4 USB Devices Enabled: None...
Page 102 Advanced Setup MX8 Technical Reference Available options are: Disabled 2 USB Ports All USB Ports Legacy USB Support This option allows you to enable support for older USB devices. The Auto option disables legacy support if no USB devices are connected.
Page 103 MX8 Technical Reference Advanced Setup Available options are: HiSpeed FullSpeed Chassis Plans 4-27...
Page 105: Pci Plug And Play Setup
MX8 Technical Reference PCI Plug and Play Setup Chapter 5 PCI Plug and Play Setup PCI P When you select PCIPnP from the BIOS Setup Utility Main Menu, the following Setup LUG AND screen displays: ETUP BIOS SETUP UTILITY Main...
Page 106 PCI Plug and Play Setup MX8 Technical Reference _______________________________________________________________________ NOTE: The values on the PCIPnP Setup screen do not necessarily reflect the values appropriate for your SBC. Refer to the explanations below for specific instructions about entering correct information. _______________________________________________________________________...
Page 107 MX8 Technical Reference PCI Plug and Play Setup Available options are: Allocate IRQ to PCI VGA This option allows you to assign an IRQ to a PCI VGA card if the card requests an IRQ. The Setup screen displays the system option:...
Page 108 PCI Plug and Play Setup MX8 Technical Reference OffBoard PCI/ISA IDE Card This option specifies the PCI expansion slot on the SBC where the off-board PCI IDE controller is installed, if any. The Setup screen displays the system option: OffBoard PCI/ISA IDE Card...
Page 109 MX8 Technical Reference PCI Plug and Play Setup The Setup screen displays the system option: Onboard (Intel 82547GI) LAN [Enabled] Available options are: Disabled Enabled Onboard (Intel 82540) LAN ® This option specifies whether or not the Intel 82540 on-board Ethernet controller is to be used.
Page 110 PCI Plug and Play Setup MX8 Technical Reference IRQ3/IRQ4/IRQ5/IRQ7/IRQ9/IRQ10/IRQ11/IRQ14/IRQ15 These options indicate whether the specified interrupt request (IRQ) is available for use by the system for PCI/Plug and Play devices or is reserved for use by legacy devices. This allows you to specify IRQs for use by legacy ISA adapter cards.
Page 111 MX8 Technical Reference PCI Plug and Play Setup Available options are: Disabled Reserved Memory Address This option specifies the beginning address (in hexadecimal) of the ROM memory area reserved for use by legacy ISA devices. If the Reserved Memory Size option is set to Disabled, this option is not available.
Page 113: Boot Setup
MX8 Technical Reference Boot Setup Chapter 6 Boot Setup When you select Boot from the BIOS Setup Utility Main Menu, the following Setup ETUP screen displays: BIOS SETUP UTILITY Main Advanced PCIPnP |Boot| Security Chipset Exit Boot Settings Configure Settings _____________________________________________ during System Boot.
Page 114 Boot Setup MX8 Technical Reference Boot Settings Configuration The options on the Boot Settings Configuration subscreen allow you to set up or modify parameters for boot procedures. The following options may be modified: • Quick Boot • Quiet Boot •...
Page 115: Boot Settings Configuration
MX8 Technical Reference Boot Setup When you select Boot Settings Configuration from the Boot Setup Menu, the following ETTINGS Setup screen displays: ONFIGURATION BIOS SETUP UTILITY |Boot| Boot Settings Configuration Allows BIOS to skip _____________________________________________ certain tests while booting. This will...
Page 116 Boot Setup MX8 Technical Reference Available options are: Disabled Enabled Quiet Boot This option specifies what will be displayed on the screen while the system is performing the POST routines when the computer is powered on or a soft reboot is performed.
Page 117 MX8 Technical Reference Boot Setup PS/2 Mouse Support This option indicates whether or not a PS/2-type mouse is supported. The Setup screen displays the system option: PS/2 Mouse Support [Auto] Available options are: Auto Disabled Enabled Wait For ’F1’ If Error Before the system boots up, the AMIBIOS executes the Power-On Self Test (POST) routines, a series of system diagnostic routines.
Page 118 Boot Setup MX8 Technical Reference Interrupt 19 Capture This option allows option ROMs to trap Interrupt 19. The Setup screen displays the system option: Interrupt 19 Capture [Disabled] Available options are: Disabled Enabled Chassis Plans...
Page 119: Boot Device Priority
MX8 Technical Reference Boot Setup When you select Boot Device Priority from the Boot Setup Menu, a Setup screen EVICE similar to the following displays: RIORITY BIOS SETUP UTILITY |Boot| Boot Device Priority Specifies the boot _______________________________________________ sequence from the available devices.
Page 120 Boot Setup MX8 Technical Reference The Setup screen displays the system option(s): ### Boot Device [xxxxxxxxx] where ### is the boot order and xxxxxxxxx is the description of the device. _______________________________________________________________________ NOTE: Disabled is also available as an option if you do not want a particular device to be included in the boot sequence.
Page 121: Hard Disk Drives
MX8 Technical Reference Boot Setup When you select Hard Disk Drives from the Boot Setup Menu, a Setup screen similar to RIVES the following displays: BIOS SETUP UTILITY |Boot| Hard Disk Drives Specifies the boot _____________________________________________ sequence from the available devices.
Page 122 Boot Setup MX8 Technical Reference Disabled is also available as an option if you do not want a particular drive to be included in the boot sequence. The Setup screen displays the system option(s): ### Drive [xxxxxxxxx] where ### is the boot order and xxxxxxxxx is the description of the hard disk drive.
Page 123: Removable Drives
MX8 Technical Reference Boot Setup When you select Removable Drives from the Boot Setup Menu, a Setup screen similar EMOVABLE to the following displays: RIVES BIOS SETUP UTILITY |Boot| Removable Drives Specifies the boot ___________________________________________ sequence from the available devices.
Page 124 Boot Setup MX8 Technical Reference Disabled is also available as an option if you do not want a particular device to be included in the boot sequence. The Setup screen displays the system option(s): ### Drive [xxxxxxxxx] where ### is the boot order and xxxxxxxxx is the description of the removable drive.
Page 125: Cd/Dvd Drives
MX8 Technical Reference Boot Setup CD/DVD D When you select CD/DVD Drives from the Boot Setup Menu, a Setup screen similar to RIVES the following displays: BIOS SETUP UTILITY |Boot| CD/DVD Drives Specifies the boot _____________________________________________ sequence from the available devices.
Page 126 Boot Setup MX8 Technical Reference Disabled is also available as an option if you do not want a particular drive to be included in the boot sequence. The Setup screen displays the system option: ### Drive [xxxxxxxxx] where ### is the boot order and xxxxxxxxx is the description of the CDROM or DVD drive.
Page 127: Chipset Setup
MX8 Technical Reference Chipset Setup Chapter 7 Chipset Setup When you select Chipset from the BIOS Setup Utility Main Menu, the following Setup HIPSET ETUP screen displays: BIOS SETUP UTILITY Main Advanced PCIPnP Boot Security |Chipset| Exit Advanced Chipset Settings Options for NB.
Page 128 Chipset Setup MX8 Technical Reference NorthBridge Configuration The options on the NorthBridge Configuration subscreen allow you to set up or modify parameters to configure the Intel SouthBridge chip. The following options may be modified: • DRAM Frequency • Configure DRAM Timing by SPD •...
Page 129: Northbridge Configuration
MX8 Technical Reference Chipset Setup When you select NorthBridge Configuration from the Chipset Setup Screen, the ORTH RIDGE following Setup screen displays: ONFIGURATION BIOS SETUP UTILITY |Chipset| NorthBridge Chipset Configuration _____________________________________________ DRAM Frequency [Auto] Configure DRAM Timing by SPD [Enabled]...
Page 130 Chipset Setup MX8 Technical Reference Configure DRAM Timing by SPD The Setup screen displays the system option: Configure DRAM Timing by SPD[ Enabled] Available options are: Disabled Enabled If you select Disabled, the following options and their default values are added to the...
Page 131 MX8 Technical Reference Chipset Setup DRAM RAS# to CAS# Delay If the Configure DRAM Timing by SPD option described above is set to Enabled, this option is not available. The Setup screen displays the system option: DRAM RAS# to CAS# Delay...
Page 132 Chipset Setup MX8 Technical Reference Available options are: Disabled Memory Hole The Setup screen displays the system option: Memory Hole [Disabled] Available options are: Disabled 15MB-16MB Primary Graphics Adapter This option may be used to select which graphics controller is to be used as the primary boot device.
Page 133 MX8 Technical Reference Chipset Setup C.S.A. Gigabit Ethernet The Setup screen displays the system option: C.S.A. Gigabit Ethernet [Auto] Available options are: Disabled Auto Chassis Plans...
Page 134 Chipset Setup MX8 Technical Reference This page intentionally left blank. Chassis Plans...
Page 135: Southbridge Configuration
MX8 Technical Reference Chipset Setup When you select SouthBridge Configuration from the Chipset Setup Screen, the OUTH RIDGE following Setup screen displays: ONFIGURATION BIOS SETUP UTILITY |Chipset| CPU BIST Enable [Enabled] MPS Revision [1.4] ←→ Select Screen ↑↓ Select Item...
Page 136 Chipset Setup MX8 Technical Reference MPS Revision The Setup screen displays the system option: MPS Revision [1.4] Available options are: Copyright 2004 by Trenton Technology Inc. All rights reserved. 7-10 Chassis Plans...
Page 137: Appendix Abios Messages
MX8 Technical Reference Appendix A BIOS Messages BIOS B Errors may occur during the POST (Power-On Self Test) routines which are performed ODES each time the system is powered on. Non-fatal errors are those which, in most cases, allow the system to continue the bootup process.
Page 138: Bios Error Messages
MX8 Technical Reference BIOS E If a non-fatal error occurs during the POST routines performed each time the system is RROR powered on, the error message will appear on the screen in the following format: ESSAGES ERROR Message Line 1...
Page 139 MX8 Technical Reference BIOS E BOOT ERRORS (continued) RROR ESSAGES CONTINUED Message Description A: Drive Error The BIOS attempted to configure the A: drive during POST, but was unable to properly configure the device. This may be due to a bad cable or faulty diskette drive.
Page 140 MX8 Technical Reference BIOS E VIRUS RELATED ERRORS RROR ESSAGES CONTINUED Message Description The following messages only display if Virus Detection is enabled in the BIOS Setup Utility. BootSector Write !! The BIOS has detected software attempting to write to a drive’s boot sector.
Page 141 MX8 Technical Reference BIOS E SYSTEM CONFIGURATION ERRORS (continued) RROR ESSAGES CONTINUED Message Description Timer Error Indicates an error while programming the count register of channel 2 of the 8254 timer. This may indicate a problem with system hardware. Interrupt Controller-1 Error BIOS POST could not initialize the Master Interrupt Controller.
Page 142: Bootblock Initialization Code Checkpoints
MX8 Technical Reference The Bootblock initialization code sets up the chipset, memory and other components OOTBLOCK before system memory is available. The following table describes the type of check- NITIALIZATION points that may occur during the Bootblock initialization portion of the BIOS:...
Page 143: Bootblock Recovery Code Checkpoints
MX8 Technical Reference The Bootblock recovery code gets control when the BIOS determines that a BIOS OOTBLOCK recovery needs to occur because the user has forced the update or the BIOS checksum is ECOVERY HECKPOINTS corrupt. The following table describes the type of checkpoints that may occur during the...
Page 144: Post Code Checkpoints
MX8 Technical Reference The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The following table describes the type of checkpoints that may occur during the HECKPOINTS POST portion of the BIOS: Check- point Description Disable NMI, parity, video for EGA and DMA controllers.
Page 145 MX8 Technical Reference HECKPOINTS Check- CONTINUED point Description Initialize different devices through DIM. See DIM Code Checkpoints section of this appendix for more information. Initialize DMAC-1 and DMAC-2. Initialize RTC date/time. Test for total memory installed in the system. Also, check for DEL or ESC keys to limit memory test.
Page 146: Dim Code Checkpoints
MX8 Technical Reference HECKPOINTS Check- CONTINUED point Description Display system configuration screen if enabled. Initialize the processor before boot, which includes the programming of the MTRRs. Prepare processor for OS boot, including final MTRR values. Wait for user input at configuration display if needed.
Page 147: Additional Checkpoints
MX8 Technical Reference While control is in the different functions, additional checkpoints are output to Port 80H DDITIONAL as word values to identify the routines being executed. HECKPOINTS The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two sets of information.

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