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Chassis Plans JXT6966 Hardware Technical Reference

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JXT6966 / JXTS6966
S6966-xxx
Revision A
HARDWARE
TECHNICAL REFERENCE
Intel® Xeon® C5500-series
Quad Core
PROCESSOR-BASED
SHB

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Summary of Contents for Chassis Plans JXT6966

  • Page 1 JXT6966 / JXTS6966 S6966-xxx Revision A HARDWARE TECHNICAL REFERENCE Intel® Xeon® C5500-series Quad Core PROCESSOR-BASED...
  • Page 2 In no event shall Chassis Plans be liable for any defect in hardware or software or loss or inadequacy of data of any kind, or for any direct, indirect, incidental or consequential damages arising out of or in connection with the performance or use of the product or information provided.
  • Page 3 This manual is as complete and factual as possible at the time of printing; however, the information in this manual may have been updated since that time. Chassis Plans reserves the right to change the functions, features or specifications of their products at any time, without notice.
  • Page 4 This page intentionally left blank...

  • Page 5: Table Of Contents

    PCI EXPRESS BACKPLANE USAGE ................4-1 Introduction ............................... 4-1 SHB Edge Connectors ............................. 4-1 Off-Board Video Card Usage ........................... 4-3 JXT6966 & JXTS6966 and Compatible Chassis Plans Backplanes ............. 4-3 2U Butterfly Backplanes ..........................4-3 Multi-Segment Backplanes ..........................4-3 Combo Backplanes ............................4-3 Server-Class Backplanes ..........................
  • Page 6 JXT6966 / JXTS6966 Technical Reference CHAPTER 5 I/O EXPANSION BOARDS – IOB33 & PEX10 ..............5-1 IOB33 Overview ..............................5-1 IOB33 Models ..............................5-1 Model # Model Name Description ......................5-1 IOB33 Features ..............................5-2 IOB33 Temperature/Environment ........................5-2 IOB33 (S7015-xxx) Block Diagram ........................5-2 IOB33 (S7015-xxx) Layout Diagram ........................
  • Page 7 JXT6966 / JXTS6966 Technical Reference ANDLING RECAUTIONS WARNING: This product has components which may be damaged by electrostatic discharge. To protect your system host board (SHB) from electrostatic damage, be sure to observe the following precautions when handling or storing the board: Keep the SHB in its static-shielded bag until you are ready to perform your installation.

  • Page 8: Before You Begin

    JXT6966 / JXTS6966 Technical Reference Before You Begin NTRODUCTION It is important to be aware of the system considerations listed below before installing your JXT6966 or JXTS6966 (S6966-xxx) SHB. Overall system performance may be affected by incorrect usage of these features.
  • Page 9 Express links built into the SHB’s processors. Chassis Plans recommends using a combo-class PICMG 1.3 backplane such as the Chassis Plans BPC7009 or BPC7041 with the SHBs in order to ensure the use of all available backplane option card slots. See Appendix C, PCI Express Backplane Usage for more details.
  • Page 10 JXT6966 / JXTS6966 Technical Reference This page intentionally left blank CHASSIS PLANS...

  • Page 11: Chapter 1 Specifications

    PCIe links out of CPU1 and the additional link out of the Intel® 3420 Platform Controller Hub (PCH). CPU2 on the JXT6966 provides four additional x4 PCI Express 2.0 or 1.1 links to a backplane via an optional plug-in card called the Chassis Plans PEX10. These extra links provide added bandwidth to systems equipped with a backplane such as the Chassis Plans BPC7009 or BPC7041.

  • Page 12: Single-Processor Models

    (PICMG) 1.3 Specifiction Direct PCI Express® 2.0 links into the Intel® Xeon® C5500 Processors  JXT6966 provides a total of 37 lanes of PCI Express for off-board system integration  Direct DDR3-1333 Memory Interfaces into the Intel® Xeon® C5500 Processors ...

  • Page 13: Jxt6966 (S6966-Xxx) - Dual-Processor Shb Block Diagram

    JXT6966 / JXTS6966 Technical Reference Specifications JXT6966 (S6966-xxx) – Dual-Processor SHB Block Diagram CHASSIS PLANS...

  • Page 14: Jxt6966 (S6966-Xxx) - Dual-Processor Shb Layout Diagram

    Specifications JXT6966 / JXTS6966 Technical Reference JXT6966 (S6966-xxx) – Dual-Processor SHB Layout Diagram CHASSIS PLANS...

  • Page 15: Jxts6966 (S6966-Xxx) - Single-Processor Shb Block Diagram

    JXT6966 / JXTS6966 Technical Reference Specifications JXTS6966 (S6966-xxx) – Single-Processor SHB Block Diagram CHASSIS PLANS...

  • Page 16: Jxts6966 (S6966-Xxx) - Single-Processor Shb Layout Diagram

    Specifications JXT6966 / JXTS6966 Technical Reference JXTS6966 (S6966-xxx) – Single-Processor SHB Layout Diagram CHASSIS PLANS...

  • Page 17: Processor

    This full duplex interface operates at 10Gb/s in each direction and provides data communications between the PCH and processor. On a dual-processor, JXT6966 the first CPU connects to the PCH and the second CPU feeds its information to the PCH via the first CPU’s DMI link.

  • Page 18: Ddr3-1333 Memory

    Each processor on the SHB supports three separate DDR3-1333 memory interfaces. There are six active Mini-DIMM sockets on the JXT6966 models and each one can support up to 32GB DIMMs for a total possible DDR3 system memory capacity of 192GB. The single processor models support three active...

  • Page 19: Pci Express Interfaces

    Specifications PCI Express Interfaces The PCI Express® links on the JXT6966 connect directly to the processors. These links can operate as either PCI Express 2.0 or PCI Express 1.1 links based on the end-point devices on the backplane that are connected to the SHB.

  • Page 20: Power Fail Detection

    Intel Xeon LV C5500 JXTS6966 2.13GHz 0.72A 6.33A 2.07A Quad-Core (LC5528) (Single CPU) Tolerance for all voltages is +/- 5% *12GB (6, 2GB DDR3 Mini-DIMMs) for a dual-processor JXT6966 and 6GB (3, 2GB DDR3 Mini- DIMMs) for a single-processor JXTS6966 CHASSIS PLANS 1-10...

  • Page 21: Temperature/Environment

    This SHB is a UL recognized product listed in file #E208896 when integrated into an industrial computer such as the Chassis Plans C5000. This board was investigated and determined to be in compliance under the Bi-National Standard for Information Technology Equipment. This included the Electrical Business Equipment, UL 1950, Third Edition, and CAN/CSA C22.22 No.

  • Page 22: Configuration Jumpers

    CAUTION: Installing this jumper is only done for special board operations such as changing the PCI Express link bifurcation operation. Contact Chassis Plans tech support before installing this jumper to prevent any unintended system operation. Password Clear (two position jumper) Install for one power-up cycle to reset the password to the default (null password).

  • Page 23: P4A/P4B Ethernet Leds And Connectors

    JXT6966 / JXTS6966 Technical Reference Specifications P4A/P4B Ethernet LEDs and Connectors I/O bracket houses the two RJ-45 network connectors for Ethernet LAN1and LAN2. Each LAN interface connector has two LEDs that indicate activity status and Ethernet connection speed. Listed below...

  • Page 24: System Bios Setup Utility

    JXT6966 & JXTS6966 POST Code LEDs System BIOS Setup Utility The JXT6966 and JXTS6966 feature the Aptio® 4.x BIOS from American Megatrends, Inc. (AMI) with a ROM-resident setup utility called the Aptio Text Setup Environment or TSE. The TSE setup utility allows...

  • Page 25: Connectors

    JXT6966 / JXTS6966 Technical Reference Specifications Connectors NOTE: Pin 1 on the connectors is indicated by the square pad on the PCB. Video Interface Connector 15 pin connector, Kycon K31X-E15S-N Signal Signal Signal Green EEDI Blue HSYNC VSYNC EECS Note: 1 –...
  • Page 26 Specifications JXT6966 / JXTS6966 Technical Reference Connectors (Continued) Reset Connector 2 pin single row header, Amp #640456-2 Signal Signal Reset In Hard Drive LED Connector 4 pin single row header, Amp #640456-4 Signal LED+ LED- LED- LED+ Dual Universal Serial Bus (USB) Connector...
  • Page 27 JXT6966 / JXTS6966 Technical Reference Specifications Connectors (Continued) P27, SATA II 300 Ports P28, 7 pin vertical connector, Molex #67491-0031 P31, P32, P35, Signal Notes: 1 – P27 = SATA0 interface, P28 = SATA1 interface, P31 = SATA2 interface, P32 = SATA3 interface, P35 = SATA4 interface, P36 = SATA5 interface 2 –...
  • Page 28 Specifications JXT6966 / JXTS6966 Technical Reference Connectors (Continued) I/O Expansion Mezzanine Card Connector 76 pin controlled impedance connector, Samtec #MIS-038-01-FD-K Signal Signal +5V_STANDBY HDA_SDIN2 +5V_STANDBY HDA_SDIN1 +5V_DUAL HDA_SDIN0 +5V_DUAL HDA_SYNC HDA_BITCLK HDA_SDOUT HDA_ACRST ICH_SMI# ICH_RCIN# ICH_SIOPME# ICH_A20GATE L_FRAME# L_AD3 L_DRQ1#...
  • Page 29 P1_PE_TXN11 P1_PE_RXN11 P1_PE_TXP12 P1_PE_RXP12 P1_PE_TXN12 P1_PE_RXN12 P1_PE_TXP13 P1_PE_RXP13 P1_PE_TXN13 P1_PE_RXN13 P1_PE_TXP14 P1_PE_RXP14 P1_PE_TXN14 P1_PE_RXN14 P1_PE_TXP15 P1_PE_RXP15 P1_PE_TXN15 P1_PE_RXN15 Note: 1 – Need CPU2 installed for PCIe GEN 2.0 link expansion via the Chassis Plans PEX10 option module. 1-19 CHASSIS PLANS...
  • Page 30 Specifications JXT6966 / JXTS6966 Technical Reference This page intentionally left blank CHASSIS PLANS 1-20...

  • Page 31: Chapter 2 Pci Express® Reference

    JXT6966 / JXTS6966 Technical Reference PCI Express Reference Chapter 2 PCI Express® Reference Introduction PCI Express is a high-speed, high-bandwidth interface with multiple channels (lanes) bundled together ® with each lane using full-duplex, serial data transfers with high clock frequencies.

  • Page 32: Shb Configurations

    ® SHB Configurations The JXT6966 and JXTS6966 are combo class SHBs that support either PCI Express server-class or graphics-class backplane configurations. Server applications require multiple, high-bandwidth PCIe links, and therefore the server-class SHB/backplane configuration is identified by multiple x8 and x4 links to the SHB edge connectors.

  • Page 33: Pci Express Edge Connector Pin Assignments

    PCI Express Reference PCI Express Edge Connector Pin Assignments Chassis Plans’ JXT6966/JXTS6966 SHB uses edge connectors A, B and C. Optional I/O signals are defined in the PICMG 1.3 specification and if implemented must be located on edge connector C of the SHB.
  • Page 34 PCI Express Reference JXT6966 / JXTS6966 Technical Reference Connector A Connector B Connector C Connector D (Not Available ) Side B Side A Side B Side A Side B Side A Side B Side A SMCLK SMBDAT +5VSBY +5VSBY USBP0+...
  • Page 35 JXT6966 / JXTS6966 Technical Reference PCI Express Reference Connector A Connector B Connector C Connector D (Not Available) Side B Side A Side B Side A Side B Side A Side B Side A REFCLK2# A_PE_TXP15 GND PLOCK# STOP# REFCLK2...

  • Page 36: Pci Express Signals Overview

    PCI Express Reference JXT6966 / JXTS6966 Technical Reference PCI Express Signals Overview The following table provides a description of the SHB slot signal groups on the PCI Express connectors. Type Signals Description Connector Source Global GND, +5V, +3.3V, +12V Power...

  • Page 37: Optional Pci Express Link Expansion

    PCI Express Reference Optional PCI Express Link Expansion An optional Chassis Plans PEX10 module may be used with the JXT6966 SHB to provide additional PCIe links to a backplane equipped with a PEX10 expansion slot. The Chassis Plans BPC7009 and BPC7041 backplane feature this PEX10 option slot.

  • Page 39: Chapter 3 Jxt6966 / Jxts6966 System Power Connections

    1.3 specification supports soft power control signals via the Advanced Configuration and ® Power Interface (ACPI). Chassis Plans SHBs support these signals, which are controlled by the ACPI and are used to implement various sleep modes. Refer to the General ACPI Configuration section of the Advanced Setup chapter in this manual for information on ACPI BIOS settings.

  • Page 40: Electrical Connection Configurations

    Chassis Plans PICMG 1.3 backplane monitors the 5VSB power signal; “green” indicates that the 5VSB signal is present. Chassis Plans backplane LEDs monitor all DC power signals, and all of the LEDs should be off before adding or removing components. Removing boards under power may result in system damage.
  • Page 41 JXT6966 / JXTS6966 Technical Reference Power Connection Legacy Non-ACPI Connection For system integrators that either do not have or do not require an ACPI compliant power supply as described in the section above, an alternative electrical configuration is described in the table on the following page.
  • Page 42 Power Connection JXT6966 / JXTS6966 Technical Reference This page intentionally left blank CHASSIS PLANS...

  • Page 43: Chapter 4 Pci Express Backplane Usage

    IOB33 routes this x1 PCI Express link down to a physical x4 PCIe edge connector on the board. A x4 connector is used so that the IOB33 can be used on other Chassis Plans SHBs that may support a x4 PCIe expansion link rather than a x1.
  • Page 44 PCI Express Backplane Usage JXT6966 / JXTS6966 Technical Reference chipset. The IOB33 edge connector mates with a backplane’s PCIe Expansion slot. This extra link is useful in supporting an additional system card slot. Refer to the IOB Expansion Board - Appendix D for more information the IOB33 and the PCI Express Reference chapter for more information on the PCI Express signal routings to the SHB edge connectors.

  • Page 45: Off-Board Video Card Usage

    If the system design requires an off-board video card, then the card must be placed in a backplane slot driven with PCI Express links from the JXT6966’s first processor. This is an Aptio® 4.x BIOS limitation that may be corrected in future software revisions. Listed below are the acceptable BPC7009 and BPC7041...
  • Page 46 PCI Express Backplane Usage JXT6966 / JXTS6966 Technical Reference CHASSIS PLANS...
  • Page 47 JXT6966 / JXTS6966 Technical Reference PCI Express Backplane Usage This page intentionally left blank CHASSIS PLANS...

  • Page 49: Chapter 5 I/O Expansion Boards - Iob33 & Pex10

    PICMG 1.3 backplane. The electrical width of this expansion link is determined by the board’s chipset. For example, an IOB33 used with a Chassis Plans MCX/MCG will route a x4 PCIe link from the south bridge of these SHBs down to a backplane. This extra link is useful in supporting an additional system card slot.

  • Page 50: Iob33 Features

    IOB33 Features IOB33 (7015-004, 7015-002, 7015-001)  I/O plate versions for a variety of Chassis Plans system host boards Two serial ports and PS/2 mouse/keyboard mini DIN on the I/O bracket  PS/2 mouse, keyboard, parallel port and floppy drive connectors ...

  • Page 51: Iob33 (S7015-Xxx) Layout Diagram

    JKXT6966 / JXTS6966 Technical Reference I/O Expansion Boards IOB33 (S7015-xxx) Layout Diagram IOB33 (S7015-xxx) I/O Plate Diagram CHASSIS PLANS...

  • Page 52: Iob33 Connectors

    I/O Expansion Boards JXT6966 / JXTS6966 Technical Reference IOB33 Connectors NOTE: Pin 1 on the connectors is indicated by the square pad on the PCB. Serial Port Connector 9 position “D” right angle, Spectrum #56-402-001 Signal Signal Carrier Detect Data Set Ready-I...
  • Page 53 Signal Kbd Clock Kbd Data Kbd Gnd Kbd Power (+5V fused) with self resetting fuse PS/2 Mouse Header 6 pin single row header, Amp #640456-6 Signal Ms Data Reserved Power (+5V fused) with self-resetting fuse Ms Clock Reserved CHASSIS PLANS...

  • Page 54: Iob33 Connectors (Continued)

    I/O Expansion Boards JXT6966 / JXTS6966 Technical Reference IOB33 C ONNECTORS CONTINUED Impedance Connector 76 pin controlled impedance connector, Samtec #MIS-038-01-FD-K Signal Signal +5V_STANDBY +5V_STANDBY +5V_DUAL +5V_DUAL ICH_SMI# ICH_RCIN# ICH_SIOPME# ICH_A20GATE L_FRAME# L_AD3 L_DRQ1# L_AD2 L_DRQ0# L_AD1 SERIRQ L_AD0 PCLK14SIO...

  • Page 55: Pex10 Overview

    PEX10 is an optional PCI Express expansion board that makes these addition 16 links available to the system designer. The PEX10 is a passive board that mounts to the back of a Chassis Plans JXT6966. This PEX10 passive interface card routes the four additional PCIe 2.0 x4 electrical links from second processor on a JXT6966 down to a mechanical x16 PCIe link expansion slot on the backplane.
  • Page 56 I/O Expansion Boards JXT6966 / JXTS6966 Technical Reference This page intentionally left blank CHASSIS PLANS...

  • Page 57: Appendix Abios Messages

    JXT6966 / JXTS6966 Technical Reference BIOS Messages Appendix A BIOS Messages Introduction A status code is a data value used to indicate progress during the boot phase. These codes are outputed to I/O port 80h on the SHB. Aptio 4.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing.

  • Page 58: Dxe Beep Codes

    BIOS Messages JXT6966 / JXTS6966 Technical Reference DXE Beep Codes # of Beeps Description Some of the Architectural Protocols are not available No Console Output Devices are found No Console Input Devices are found Invalid password Flash update is failed...

  • Page 59: Bios Status Codes

    The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The following chart is a key to interpreting the POST codes displayed on LEDs 0 through 7 on the JXT6966 and JXTS6966 SHBs. Refer to the board layout in the Specifications chapter for the exact location of the POST code LEDs.

  • Page 60: Status Code Ranges

    BIOS Messages JXT6966 / JXTS6966 Technical Reference Status Code Ranges Status Code Range Description 0x01 – 0x0F SEC Status Codes & Errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 –...
  • Page 61 JXT6966 / JXTS6966 Technical Reference BIOS Messages PEI Status Codes Status Code Description Progress Codes 0x10 PEI Core is started 0x11 Pre-memory CPU initialization is started 0x12 Pre-memory CPU initialization (CPU module specific) 0x13 Pre-memory CPU initialization (CPU module specific)
  • Page 62 BIOS Messages JXT6966 / JXTS6966 Technical Reference PEI Error Codes 0x50 Memory initialization error. Invalid memory type or incompatible memory speed 0x51 Memory initialization error. SPD reading has failed 0x52 Memory initialization error. Invalid memory size or memory modules do not match.

  • Page 63: Pei Beep Codes

    JXT6966 / JXTS6966 Technical Reference BIOS Messages PEI Beep Codes # of Beeps Description Memory not Installed Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) Recovery started DXEIPL was not found DXE Core Firmware Volume was not found...
  • Page 64 BIOS Messages JXT6966 / JXTS6966 Technical Reference 0x7A – 0x7F Reserved for future AMI DXE codes 0x80 – 0x8F OEM DXE initialization codes 0x90 Boot Device Selection (BDS) phase is started 0x91 Driver connecting is started 0x92 PCI Bus initialization is started...

  • Page 65: Dxe Beep Codes

    JXT6966 / JXTS6966 Technical Reference BIOS Messages 0xB8 – 0xBF Reserved for future AMI codes 0xC0 – 0xCF OEM BDS initialization codes DXE Error Codes 0xD0 CPU initialization error 0xD1 North Bridge initialization error 0xD2 South Bridge initialization error 0xD3...

  • Page 66: Acpi/Asl Status Codes

    BIOS Messages JXT6966 / JXTS6966 Technical Reference ACPI/ASL Status Codes Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state...

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