Chip Configuration - Asus A7A266 User Manual

4.4.1 Chip Configuration

SDRAM Configuration [By SPD]
This sets the optimal timings for items 4-7, depending on the memory mod-
ules that you are using. The default setting [By SPD] configures items 4-7
by reading the contents in the SPD (Serial Presence Detect) device. The
EEPROM on the memory module stores critical parameter information
about the module, such as memory type, size, speed, voltage interface, and
module banks. Configuration options: [User Define] [By SPD]
NOTE: The following 3 fields will only be adjustable when SDRAM Con-
figuration is set to [User Define].
SDRAM CAS Latency
This controls the latency between the SDRAM read command and the
time that the data actually becomes available.
SDRAM RAS to CAS Delay
This controls the latency between the SDRAM active command and
the read/write command.
SDRAM RAS Precharge Time
This controls the idle clocks after issuing a precharge command to the
SDRAM.
SDRAM Cycle Time (Tras, Trc) [6T, 8T]
This feature controls the number of SDRAM clocks used for SDRAM pa-
rameters Tras and Trc. Tras specifies the minimum clocks required be-
tween active command and precharge command. Trc specifies the mini-
mum clocks required between active command and re-active command.
Configuration options: [5T, 7T] [6T, 8T]
4. BIOS SETUP
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