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• BD BOARD IC121 CXD2652AR
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK
PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
Pin No.
Pin Name
I/O
1
FOK
O
2
SHCK
O
3
XBUSY
O
4
SLOC
O
5
SWDT
6
SCLK
I (S)
7
XLAT
I (S)
8
SRDT
O (3)
9
SENS
O (3)
10
XRST
I (S)
11
SQSY
O
12
DQSY
O
13
RECP
14
XINT
O
15
TX
16
OSCI
17
OSCO
O
TE
L 13942296513
18
XTSL
19
TEST G
—
20
RVSS
—
21
DIN
22
DOUT
O
23
ADDT
24
DADT
O
25
LRCK
O
26
XBCK
O
27
FS256
O
28
DVDD
—
29
A03
O
30
A02
O
31
A01
O
32
A00
O
33
A10
O
34
A04
O
35
A05
O
36
A06
O
37
A07
O
38
A08
O
39
A11
O
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* I (A) for analog input, O (3) for 3-state output, I (S) for schmitt input, and O (A) for analog output in the column I/O.
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Focus OK signal output to the mechanism controller (IC100) "H" is output when focus is on
Track jump detection signal output to the mechanism controller (IC100)
Monitor 2 signal output to the mechanism controller (IC100)
Monitor 3 signal output to the mechanism controller (IC100)
I
Writing data signal input from the mechanism controller (IC100)
Serial clock signal input from the mechanism controller (IC100)
Serial latch signal input from the mechanism controller (IC100)
Reading data signal output to the mechanism controller (IC100)
Internal status (SENSE) output to the mechanism controller (IC100)
Reset signal input from the mechanism controller (IC100) "L":reset
Subcode Q sync (SCOR) output to the mechanism controller (IC100)
"L" is output every 13.3 msec Almost all, :H: is output
Digital In U-bit CD format subcode Q sync (SCOR) output to the mechanism controller (IC100)
"L" is output every 13.3 msec Almost all, "H" is output
Laser power selection signal input from the mechanism controller (IC100)
I
"H": recording mode, "L": playback mode
Interrupt status output to the mechanism controller (IC100)
Recording data output enable signal input from the mechanism controller (IC100)
I
Writing data transmission timing input (Also serves as the magnetic head on/off output)
I
System clock signal (512Fs=22.5792 MHz) input from the A/D, D/A converter (IC202)
System clock signal (512Fs=22.5792 MHz) output terminal (Not used)
Input terminal for the system clock frequency setting
I
"L":45.1584MHz, "H":22.5792MHz (fixed at "H" in this set)
Test pin
Ground terminal (digital system)
I
Digital audio signal input terminal when recording mode (for optical in)
Digital audio signal output terminal when playback mode (for optical out)
I
Recording data input from the A/D, D/A converter (IC202)
Playback data output to the A/D, D/A converter (IC202)
L/R clock signal (44.1kHz) output to the A/D, D/A converter (IC202)
Bit clock signal (2.8224MHz) output to the A/D, D/A converter (IC202)
Clock signal (11.2896MHz) output terminal (Not used)
Power supply terminal (+3.3V) (digital system)
Address signal output to the external D-RAM
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Description
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