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TMS320TCI6486
Texas Instruments TMS320TCI6486 Module Manuals
Manuals and User Guides for Texas Instruments TMS320TCI6486 Module. We have
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Texas Instruments TMS320TCI6486 Module manual available for free PDF download: User Manual
Texas Instruments TMS320TCI6486 User Manual (160 pages)
DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module
Brand:
Texas Instruments
| Category:
IP Access Controllers
| Size: 0.81 MB
Table of Contents
Table of Contents
3
Preface
10
Introduction
11
Purpose of the Peripheral
11
Features
11
Functional Block Diagram
12
EMAC and MDIO Block Diagram
12
Serial Management Interface Pins
13
EMAC1_EN Pin Description
13
Industry Standard(S) Compliance Statement
14
EMAC Functional Architecture
15
Clock Control
15
EMAC Clock Specifications
15
Memory Map
16
System-Level Connections
17
EMAC0 Interface Selection Pins
17
EMAC1 Interface Selection Pins
17
MACSEL0[2:0], MACSEL1[1:0], and EMAC1_EN Decoding
17
Ethernet Configuration with MII Interface
18
EMAC and MDIO Signals for MII Interface
19
Ethernet Configuration with RMII Interface
20
EMAC and MDIO Signals for RMII Interface
20
Ethernet Configuration with GMII Interface
21
EMAC and MDIO Signals for GMII Interface
22
Ethernet Configuration with RGMII Interface
23
EMAC and MDIO Signals for RGMII Interface
23
Ethernet Configuration with S3MII Interface
25
EMAC and MDIO Signals for S3MII Interface
26
S3MII Multi-PHY Configuration
27
S3MII Switch Configuration
28
Ethernet Protocol Overview
29
Ethernet Frame
29
Ethernet Frame Description
29
Programming Interface
31
Basic Descriptor Format
31
Basic Descriptors
31
Typical Descriptor Linked List
32
Transmit Descriptor Format
34
Receive Descriptor Format
37
Communications Port Programming Interface (CPPI)
40
Ethernet Multicore Interrupt Combiner (EMIC) Module
40
EMIC Block Diagram
41
Pacing Block
42
TDSM State Transition Diagram
43
DSM State Transition Diagram
44
Transmit Pacer and Interrupt Combiner
45
Receive Pacer and Interrupt Combiner
46
Management Data Input/Output (MDIO) Module
47
Common Interrupt Combiner
47
MDIO Module Block Diagram
48
EMAC Module
52
EMAC Module Block Diagram
52
2.10 Media Independent Interfaces
54
2.11 Packet Receive Operation
58
Receive Frame Treatment Summary
61
2.12 Packet Transmit Operation
62
Middle-Of-Frame Overrun Treatment
62
2.13 Receive and Transmit Latency
63
2.14 Transfer Node Priority
63
2.15 Reset Considerations
64
2.16 Initialization
65
2.17 Interrupt Support
67
2.18 Power Management
69
2.19 Emulation Considerations
69
Emulation Control
70
EMIC Module Registers
71
EW_INTCTL Registers
71
RPIC Registers
71
EW_INTCTL Register
71
RPCFG Register
72
RPCFG Register Field Descriptions
72
RPSTAT Register
73
RPSTAT Register Field Descriptions
73
TPIC Registers
74
TPCFG Register
74
TPCFG Register Field Descriptions
74
Prescalar Configuration Register (PSCFG)
75
TPSTAT Register
75
TPSTAT Register Field Descriptions
75
MDIO Registers
76
Introduction
76
Management Data Input/Output (MDIO) Registers
76
MDIO Version Register (VERSION)
77
MDIO Version Register (VERSION) Field Descriptions
77
MDIO Control Register (CONTROL)
78
MDIO Control Register (CONTROL) Field Descriptions
78
PHY Acknowledge Status Register (ALIVE)
79
PHY Acknowledge Status Register (ALIVE) Field Descriptions
79
PHY Link Status Register (LINK)
80
PHY Link Status Register (LINK) Field Descriptions
80
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
81
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions
81
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
82
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions
82
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
83
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions
83
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
84
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions
84
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
85
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions
85
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
86
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions
86
MDIO User Access Register 0 (USERACCESS0)
87
MDIO User Access Register 0 (USERACCESS0) Field Descriptions
87
MDIO User PHY Select Register 0 (USERPHYSEL0)
88
MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions
88
MDIO User Access Register 1 (USERACCESS1)
89
MDIO User Access Register 1 (USERACCESS1) Field Descriptions
89
MDIO User PHY Select Register 1 (USERPHYSEL1)
90
MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions
90
EMAC Port Registers
91
Ethernet Media Access Controller (EMAC) Registers
91
Transmit Identification and Version Register (TXIDVER)
95
Transmit Identification and Version Register (TXIDVER) Field Descriptions
95
Transmit Control Register (TXCONTROL)
96
Transmit Control Register (TXCONTROL) Field Descriptions
96
Transmit Teardown Register (TXTEARDOWN)
97
Transmit Teardown Register (TXTEARDOWN) Field Descriptions
97
Receive Identification and Version Register (RXIDVER)
98
Receive Identification and Version Register (RXIDVER) Field Descriptions
98
Receive Control Register (RXCONTROL)
99
Receive Control Register (RXCONTROL) Field Descriptions
99
Receive Teardown Register (RXTEARDOWN)
100
Receive Teardown Register (RXTEARDOWN) Field Descriptions
100
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
101
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
101
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
102
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
102
Transmit Interrupt Mask Set Register (TXINTMASKSET)
103
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
103
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
104
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
104
MAC Input Vector Register (MACINVECTOR)
105
MAC Input Vector Register (MACINVECTOR) Field Descriptions
105
MAC End-Of-Interrupt Vector Register (MACEOIVECTOR)
106
MAC End-Of-Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
106
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
107
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
107
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
108
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
108
Receive Interrupt Mask Set Register (RXINTMASKSET)
109
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
109
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
110
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
110
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
111
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
111
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
112
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
112
MAC Interrupt Mask Set Register (MACINTMASKSET)
113
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
113
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
114
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
114
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
115
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
115
Descriptions
116
Receive Unicast Enable Set Register (RXUNICASTSET)
118
Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
118
Receive Unicast Clear Register (RXUNICASTCLEAR)
119
Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
119
Receive Maximum Length Register (RXMAXLEN)
120
Receive Maximum Length Register (RXMAXLEN) Field Descriptions
120
Receive Buffer Offset Register (RXBUFFEROFFSET)
121
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
121
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
122
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
122
Receive Channel 0-7 Flow Control Threshold Register (Rxnflowthresh)
123
Receive Channel N Flow Control Threshold Register (Rxnflowthresh)
123
Receive Channel N Flow Control Threshold Register (Rxnflowthresh) Field Descriptions
123
Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer)
124
Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
124
Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions
124
MAC Control Register (MACCONTROL)
125
MAC Control Register (MACCONTROL) Field Descriptions
125
MAC Status Register (MACSTATUS)
127
MAC Status Register (MACSTATUS) Field Descriptions
127
Emulation Control Register (EMCONTROL)
129
Emulation Control Register (EMCONTROL) Field Descriptions
129
FIFO Control Register (FIFOCONTROL)
130
FIFO Control Register (FIFOCONTROL) Field Descriptions
130
MAC Configuration Register (MACCONFIG)
131
MAC Configuration Register (MACCONFIG) Field Descriptions
131
Soft Reset Register (SOFTRESET)
132
Soft Reset Register (SOFTRESET) Field Descriptions
132
MAC Source Address Low Bytes Register (MACSRCADDRLO)
133
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
133
MAC Source Address High Bytes Register (MACSRCADDRHI)
134
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
134
MAC Hash Address Register 1 (MACHASH1)
135
MAC Hash Address Register 1 (MACHASH1) Field Descriptions
135
MAC Hash Address Register 2 (MACHASH2)
136
MAC Hash Address Register 2 (MACHASH2) Field Descriptions
136
Back off Test Register (BOFFTEST)
137
Back off Test Register (BOFFTEST) Field Descriptions
137
Transmit Pacing Algorithm Test Register (TPACETEST)
138
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
138
Receive Pause Timer Register (RXPAUSE)
139
Receive Pause Timer Register (RXPAUSE) Field Descriptions
139
Transmit Pause Timer Register (TXPAUSE)
140
Transmit Pause Timer Register (TXPAUSE) Field Descriptions
140
MAC Address Low Bytes Register (MACADDRLO)
141
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
141
MAC Address High Bytes Register (MACADDRHI)
142
MAC Address High Bytes Register (MACADDRHI) Field Descriptions
142
MAC Index Register (MACINDEX)
143
MAC Index Register (MACINDEX) Field Descriptions
143
Transmit Channel 0-7 DMA Head Descriptor Pointer Register (Txnhdp)
144
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp)
144
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp) Field Descriptions
144
Receive Channel 0-7 DMA Head Descriptor Pointer Register (Rxnhdp)
145
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp)
145
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp) Field Descriptions
145
Transmit Channel 0-7 Completion Pointer Register (Txncp)
146
Transmit Channel N Completion Pointer Register (Txncp)
146
Transmit Channel N Completion Pointer Register (Txncp) Field Descriptions
146
Receive Channel 0-7 Completion Pointer Register (Rxncp)
147
Receive Channel N Completion Pointer Register (Rxncp)
147
Receive Channel N Completion Pointer Register (Rxncp) Field Descriptions
147
5.50 Network Statistics Registers
148
Statistics Register
148
Statistics Register Field Descriptions
148
Appendix A Glossary
157
Appendix B Revision History
159
EMAC/MDIO Revision History
159
Important Notice
160
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