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TMS320DM36X
Texas Instruments TMS320DM36X Manuals
Manuals and User Guides for Texas Instruments TMS320DM36X. We have
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Texas Instruments TMS320DM36X manuals available for free PDF download: User Manual
Texas Instruments TMS320DM36X User Manual (134 pages)
Digital Media System-on-Chip (DMSoC), Ethernet Media Access Controller (EMAC)
Brand:
Texas Instruments
| Category:
IP Access Controllers
| Size: 0.68 MB
Table of Contents
Table of Contents
3
Preface
10
Introduction
13
Purpose of the Peripheral
13
Features
13
Functional Block Diagram
14
EMAC and MDIO Block Diagram
14
Industry Standard(S) Compliance Statement
15
Architecture
15
Clock Control
15
Memory Map
16
Signal Descriptions
16
Ethernet Configuration MII Connections
16
Pin Multiplexing
17
EMAC and MDIO Signals for MII Interface
17
Ethernet Protocol Overview
18
Ethernet Frame Format
18
Ethernet Frame Description
18
Programming Interface
19
Basic Descriptor Format
19
Typical Descriptor Linked List
20
Basic Descriptor Description
20
Transmit Buffer Descriptor Format
23
Receive Buffer Descriptor Format
26
EMAC Control Module
30
EMAC Control Module Block Diagram
30
MDIO Module
33
MDIO Module Block Diagram
33
EMAC Module
37
EMAC Module Block Diagram
37
Media Independent Interface (MII)
40
2.11 Packet Receive Operation
44
Receive Frame Treatment Summary
47
Middle of Frame Overrun Treatment
48
2.12 Packet Transmit Operation
49
2.13 Receive and Transmit Latency
49
2.14 Transfer Node Priority
50
2.15 Reset Considerations
50
2.16 Initialization
51
2.17 Interrupt Support
55
EMAC Control Module Interrupt Logic Diagram
55
2.18 Power Management
59
2.19 Emulation Considerations
59
Emulation Control
59
EMAC Control Module Registers
60
EMAC Control Module Identification and Version Register (CMIDVER)
60
EMAC Control Module Identification and Version Register (CMIDVER) Field Descriptions
60
EMAC Control Module Software Reset Register (CMSOFTRESET)
61
EMAC Control Module Emulation Control Register (CMEMCONTROL)
61
EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions
61
EMAC Control Module Emulation Control Register (CMEMCONTROL) Field Descriptions
61
EMAC Control Module Interrupt Control Register (CMINTCTRL)
62
EMAC Control Module Interrupt Control Register (CMINTCTRL) Field Descriptions
62
EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN)
63
EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
63
EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) Field Descriptions
63
EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) Field Descriptions
63
EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
64
EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) Field Descriptions
64
EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN)
65
EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) Field Descriptions
65
EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT)
66
EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)
66
EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) Field Descriptions
66
EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) Field Descriptions
66
EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)
67
EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) Field Descriptions
67
EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT)
68
EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT)
68
EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) Field Descriptions
68
EMAC Control Module Receive Interrupts Per Millisecond Register (CMRXINTMAX)
69
EMAC Control Module Transmit Interrupts Per Millisecond Register (CMTXINTMAX)
69
EMAC Control Module Receive Interrupts Per Millisecond Register (CMRXINTMAX) Field Descriptions
69
EMAC Control Module Transmit Interrupts Per Millisecond Register (CMTXINTMAX) Field Descriptions
69
MDIO Registers
70
MDIO Version Register (VERSION)
70
Management Data Input/Output (MDIO) Registers
70
MDIO Version Register (VERSION) Field Descriptions
70
MDIO Control Register (CONTROL)
71
MDIO Control Register (CONTROL) Field Descriptions
71
PHY Acknowledge Status Register (ALIVE)
72
PHY Link Status Register (LINK)
72
PHY Acknowledge Status Register (ALIVE) Field Descriptions
72
PHY Link Status Register (LINK) Field Descriptions
72
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
73
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions
73
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
74
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions
74
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
75
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions
75
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
76
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions
76
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
77
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions
77
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
78
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions
78
MDIO User Access Register 0 (USERACCESS0)
79
MDIO User Access Register 0 (USERACCESS0) Field Descriptions
79
MDIO User PHY Select Register 0 (USERPHYSEL0)
80
MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions
80
MDIO User Access Register 1 (USERACCESS1)
81
MDIO User Access Register 1 (USERACCESS1) Field Descriptions
81
MDIO User PHY Select Register 1 (USERPHYSEL1)
82
MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions
82
Ethernet Media Access Controller (EMAC) Registers
83
Transmit Identification and Version Register (TXIDVER)
86
Transmit Control Register (TXCONTROL)
86
Transmit Identification and Version Register (TXIDVER) Field Descriptions
86
Transmit Control Register (TXCONTROL) Field Descriptions
86
Transmit Teardown Register (TXTEARDOWN)
87
Transmit Teardown Register (TXTEARDOWN) Field Descriptions
87
Receive Identification and Version Register (RXIDVER)
88
Receive Identification and Version Register (RXIDVER) Field Descriptions
88
Receive Control Register (RXCONTROL)
89
Receive Teardown Register (RXTEARDOWN)
89
Receive Control Register (RXCONTROL) Field Descriptions
89
Receive Teardown Register (RXTEARDOWN) Field Descriptions
89
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
90
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
90
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
91
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
91
Transmit Interrupt Mask Set Register (TXINTMASKSET)
92
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
92
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
93
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
93
MAC Input Vector Register (MACINVECTOR)
94
MAC End of Interrupt Vector Register (MACEOIVECTOR)
94
MAC Input Vector Register (MACINVECTOR) Field Descriptions
94
MAC End of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
94
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
95
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
95
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
96
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
96
Receive Interrupt Mask Set Register (RXINTMASKSET)
97
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
97
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
98
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
98
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
99
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
99
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
99
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
99
MAC Interrupt Mask Set Register (MACINTMASKSET)
100
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
100
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
100
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
100
Descriptions
100
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
101
Receive Unicast Enable Set Register (RXUNICASTSET)
104
Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
104
Receive Unicast Clear Register (RXUNICASTCLEAR)
105
Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
105
Receive Maximum Length Register (RXMAXLEN)
106
Receive Buffer Offset Register (RXBUFFEROFFSET)
106
Receive Maximum Length Register (RXMAXLEN) Field Descriptions
106
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
106
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
107
Receive Channel 0-7 Flow Control Threshold Register (Rxnflowthresh)
107
Receive Channel N Flow Control Threshold Register (Rxnflowthresh)
107
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
107
Receive Channel N Flow Control Threshold Register (Rxnflowthresh) Field Descriptions
107
Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer)
108
Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
108
Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions
108
MAC Control Register (MACCONTROL)
109
MAC Control Register (MACCONTROL) Field Descriptions
109
MAC Status Register (MACSTATUS)
111
MAC Status Register (MACSTATUS) Field Descriptions
111
Emulation Control Register (EMCONTROL)
113
FIFO Control Register (FIFOCONTROL)
113
Emulation Control Register (EMCONTROL) Field Descriptions
113
FIFO Control Register (FIFOCONTROL) Field Descriptions
113
MAC Configuration Register (MACCONFIG)
114
Soft Reset Register (SOFTRESET)
114
MAC Configuration Register (MACCONFIG) Field Descriptions
114
Soft Reset Register (SOFTRESET) Field Descriptions
114
MAC Source Address Low Bytes Register (MACSRCADDRLO)
115
MAC Source Address High Bytes Register (MACSRCADDRHI)
115
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
115
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
115
MAC Hash Address Register 1 (MACHASH1)
116
MAC Hash Address Register 2 (MACHASH2)
116
MAC Hash Address Register 1 (MACHASH1) Field Descriptions
116
MAC Hash Address Register 2 (MACHASH2) Field Descriptions
116
Back off Test Register (BOFFTEST)
117
Transmit Pacing Algorithm Test Register (TPACETEST)
117
Back off Random Number Generator Test Register (BOFFTEST)
117
Back off Test Register (BOFFTEST) Field Descriptions
117
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
117
Receive Pause Timer Register (RXPAUSE)
118
Transmit Pause Timer Register (TXPAUSE)
118
Receive Pause Timer Register (RXPAUSE) Field Descriptions
118
Transmit Pause Timer Register (TXPAUSE) Field Descriptions
118
MAC Address Low Bytes Register (MACADDRLO)
119
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
119
MAC Address High Bytes Register (MACADDRHI)
120
MAC Index Register (MACINDEX)
120
MAC Address High Bytes Register (MACADDRHI) Field Descriptions
120
MAC Index Register (MACINDEX) Field Descriptions
120
Transmit Channel 0-7 DMA Head Descriptor Pointer Register (Txnhdp)
121
Receive Channel 0-7 DMA Head Descriptor Pointer Register (Rxnhdp)
121
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp)
121
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp)
121
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp) Field Descriptions
121
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp) Field Descriptions
121
Transmit Channel 0-7 Completion Pointer Register (Txncp)
122
Receive Channel 0-7 Completion Pointer Register (Rxncp)
122
Transmit Channel N Completion Pointer Register (Txncp)
122
Receive Channel N Completion Pointer Register (Rxncp)
122
Transmit Channel N Completion Pointer Register (Txncp) Field Descriptions
122
Receive Channel N Completion Pointer Register (Rxncp) Field Descriptions
122
5.50 Network Statistics Registers
123
Statistics Register
123
Appendix A Glossary
131
Physical Layer Definitions
132
Appendix B Revision History
133
Document Revision History
133
Important Notice
134
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Texas Instruments TMS320DM36X User Manual (18 pages)
DMSoC Analog to Digital Converter (ADC) Interface
Brand:
Texas Instruments
| Category:
Media Converter
| Size: 0.17 MB
Table of Contents
SPRUFI7 – March
2
Table of Contents
3
Preface
5
Read this First
5
Features
8
ADC if Block Diagram
8
Industry Compliance Statement
9
Block Diagram
8
Peripheral Architecture
9
Clock Control
9
Signal Descriptions
9
Functional Operation
9
Reset Considerations
10
Interrupt Support
10
EDMA Event Support
11
Power Management
11
Emulation Considerations
11
ADC Interface Memory Map Registers
11
Adctl
12
Registers
11
ADC Control (ADCTL) Field Descriptions
12
Cmptgt
13
Cmpldat
13
ADC Control (ADCTL) Register
12
Comparator Target Channel (CMPTGT) Field Descriptions
13
Comparator Target Channel (CMPTGT) Register
13
Comparison A/D Lower Data (CMPLDAT) Field Descriptions
13
Cmpudat
14
Setdiv
14
Chsel
14
Comparison A/D Lower Data (CMPLDAT) Register
13
Comparison A/D Upper Data (CMPUDAT) Field Descriptions
14
Comparison A/D Upper Data (CMPUDAT) Register
14
Setup Divide Value for Start A/D (SETDIV) Field Descriptions
14
Ad0Dat
15
Ad1Dat
15
Setup Divide Value for Start A/D (SETDIV) Register
14
Analog Input Channel Select (CHSEL) Field Descriptions
15
A/D Conversion Data 0 (AD0DAT) Field Descriptions
15
Ad2Dat
16
Ad3Dat
16
Ad4Dat
16
A/D Conversion Data 2 (AD2DAT) Register
16
A/D Conversion Data 3 (AD3DAT) Register
16
A/D Conversion Data 4 (AD4DAT) Register
16
A/D Conversion Data 1 (AD1DAT) Field Descriptions
16
A/D Conversion Data 2 (AD2DAT) Field Descriptions
16
A/D Conversion Data 3 (AD3DAT) Field Descriptions
16
Ad5Dat
17
Emuctrl
17
A/D Conversion Data 5 (AD5DAT) Register
17
Analog Input Channel Select (CHSEL) Register
15
A/D Conversion Data 0 (AD0DAT) Register
15
A/D Conversion Data 1 (AD1DAT) Register
15
CHSEL Setting for Channel Selection
15
Emulation Control (EMUCTRL) Field Descriptions
17
Emulation Control (EMUCTRL) Register
17
A/D Conversion Data 4 (AD4DAT) Field Descriptions
17
A/D Conversion Data 5 (AD5DAT) Field Descriptions
17
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