Chipset - Asus P5GD2-VM User Manual

Enhanced C1 Control [Auto] Enhanced C1 Control [Auto] Enhanced C1 Control [Auto] Enhanced C1 Control [Auto] Enhanced C1 Control [Auto]
When set to [Auto], the BIOS will automatically check the CPU's capability
to enable the C1E support. In C1E mode, the CPU power consumption is
lower when idle. Configuration options: [Auto] [Disabled]
CPU Internal Thermal Control [Auto] CPU Internal Thermal Control [Auto]
CPU Internal Thermal Control [Auto] CPU Internal Thermal Control [Auto] CPU Internal Thermal Control [Auto]
Disables or sets the CPU internal thermal control.
Configuration options: [Auto] [Disabled]
Hyper Threading Technology [Enabled] Hyper Threading Technology [Enabled] Hyper Threading Technology [Enabled] Hyper Threading Technology [Enabled] Hyper Threading Technology [Enabled]
Allows you to enable or disable the processor Hyper-Threading Technology.
Configuration options: [Disabled] [Enabled]
2.4.3 2.4.3 2.4.3

Chipset

Chipset Chipset
2.4.3 2.4.3 Chipset Chipset
The Chipset menu allows you to change the advanced chipset settings.
Select an item then press <Enter> to display the sub-menu.
Advanced Chipset Settings
Configure DRAM Timing by SPD
Booting Graphic Adapter Priori
Internal Graphics Mode Select
Fixed Graphic Memory Size
DVT Graphic Memory Size
Advanced Chipset Settings Advanced Chipset Settings
Advanced Chipset Settings Advanced Chipset Settings Advanced Chipset Settings
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set
according to the DRAM SPD (Serial Presence Detect). When disabled,
you can manually set the DRAM timing parameters through the DRAM
sub-items. Configuration options: [Disabled] [Enabled]
The following sub-items appear when this item is Disabled.
D R A M C A S # L a t e n c y [ 5 C l o c k s ] D R A M C A S # L a t e n c y [ 5 C l o c k s ] D R A M C A S # L a t e n c y [ 5 C l o c k s ]
D R A M C A S # L a t e n c y [ 5 C l o c k s ] D R A M C A S # L a t e n c y [ 5 C l o c k s ]
Controls the latency between the SDRAM read command and the
time the data actually becomes available. Configuration options: [5
Clocks] [4 Clocks] [3 Clocks]
A S U S P 5 G D 2 - V M A S U S P 5 G D 2 - V M
A S U S P 5 G D 2 - V M A S U S P 5 G D 2 - V M A S U S P 5 G D 2 - V M
[Enabled]
[PCI Express/Int-VGA]
[Enabled, 8MB]
[32MB]
[32MB]
Enable or disable
DRAM timing.
2 - 2 1 2 - 2 1
2 - 2 1 2 - 2 1 2 - 2 1