Sanyo FISHER DVD-1500 Service Manual page 61

IC BLOCK DIAGRAM & DESCRIPTION
IC801 TC90A41AF(DATA PROCESSOR)
No. Name I/O DESCRIPTION
1 DPCK! I
Basic clock input
2 DVDD3 - Digital power source 3.3V
3 SVCK1 I
Servo basic clock input
4 SVCK0 O Servo basic clock output
5 DVSS - Digital power source 0V
6 DVDD3 - Digital power source 3.3V
7 N.C - N.C
8 HDWT I
MPU write signal
9 HDRD I
MPU read signal
10 HCEN I
MPU chip selector
11 HDO I/O MPU data buss
12 HD! I/O MPU data buss
13 HD2 I/O MPU data buss
14 HD3 I/O MPU data buss
15 HD4 I/O MPU data buss
16 HD5 I/O MPU data buss
17 HD6 I/O MPU data buss
18 HD7 I/O MPU data buss
19 DVSS - Digital power source 0V
20 DVDD5 - Digital power source 5V
21 HINT O MPU interrupt signal
22 HAO I
MPU address buss
23 HA1 I
MPU address buss
24 PLCK I/O Read channel clock input
25 ED0 - N.C
26 ED1 - N.C
27 ED2 - N.C
28 ED3 - N.C
29 ED4 - N.C
30 ED5 - N.C
31 ED6 - N.C
32 ED7 - N.C
33 TEST I
Low setting
34 PD0N O PLL phase error signal output
35 PD0P O PLL phase error signal output
36 PLLD O PLL detection result output
37 LPFN I
input for PLL loop filter
38 LPFO O output for PLL loop filter
39 VCOF O VCO filter output
40 SLCO O Basic power output for internal Comparator
41 AVSS - Analogue power source
42 AVR O Analogue power source for not PLL stem
43 VRC - Resister division point voltage
44 PVR O Analogue power source for PLL stem
45 AVDD - Analogue power source
46 BAIS - Second basic power 0V
47 RVDD - Power source 3.3V
48 RFIN I
RF signal input
49 RVSS - Power source 0V
50 RVR1 - First basic power source
IC911 BA033FP(REGULATOR)
1 2
GND
V
CC
3
OUT
No. Name I/O DESCRIPTION
51
DVR I DMO basic power source
52
DMO O Disc Equaliser output for DVD
53
RASN O External RAM address selector
54
CASN O External RAM address selector
55
MOEN O External RAM output Permission signal
56
MWEN O External RAM read/write select
57
DVSS - Digital power source 0V
58
DVDD3 - Digital power source 3.3V
59
MA9 O External RAM address bus
60
MA8 O External Ram address bus
61
MA7 O External Ram address bus
62
MA6 O External Ram address bus
63
MA5 O External Ram address bus
64
MA4 O External Ram address bus
65
MA3 O External Ram address bus
66
MA2 O External Ram address bus
67
MA1 O External Ram address bus
68
MA0 O External Ram address bus
69
DVSS - Digital power source 0V
70
DVDD5 - Digital power source 5V
71
MD7 I/O External Ram data bus
72
MD6 I/O External Ram data bus
73
MD5 I/O External Ram data bus
74
MD4 I/O External Ram data bus
75
MD3 I/O External Ram data bus
76
MD2 I/O External Ram data bus
77
MD1 I/O External Ram data bus
78
MD0 I/O External Ram data bus
79
SD7 O MPEG data output
80
SD6 O MPEG data output
81
SD5 O MPEG data output
82
SD4 O MPEG data output
83
DVSS - Digital power source 0V
84
DVDD3 - Digital power source 5V
85
SD3 O MPEG data output
86
SD2 O MPEG data output
87
SD1 O MPEG data output
88
SD0 O MPEG data output
89
SERR O MPEG data Reliability flag
90
SBGN O MPEG output sector synchronise signal
91
SENB O MPEG data effective flag
92
SDCK O MPEG data Forwarding clock
93
DVSS - Digital power source
94
SREQ I MPEG data request flag
95
RSTN I Hard reset input
96
DVDD3 - Digital power source
97
STDA O Play status monitor data
98
STCK O Play status monitor synchronies signal
99
UPWM O General purpose PWM output
100
DVSS - Digital power source 0V
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