Sanyo FISHER DVD-1500 Service Manual page 60

IC BLOCK DIAGRAM & DESCRIPTION
IC701 TC9461F(DIGITAL SERVO SIGNAL PROCESSOR)
No. Name I/O DESCRIPTION
1 VSS - Digital ground
2 BCK O Bit clock(1.4122MHz) output
3 AOUT O Audio data output
4 DOUT O Digital output
5 MBOV O Buffer memory over signal output
6 IPF O Correction flag output
7 SBOK O CRCC judgement result of subcode "Q" data output
8 CLCK I/O Clock output for subcode "P"~"W" data read
9 VDD - Digital power plus source.
10 VSS - Digital ground.
11 DATA O Subcode "P"~"W" data output.
12 SFSY O Frame synchronism signal output by play.
13 SBSY O Subcode block synchronism output
14 SPCK O Clock output for process status signal read
15 SPDA O Processor status signal output.
16 COFS O Frame clock(7.35kHz) output by amendment
17 MONIT O LSI internal signal monitor
18 VDD - Digital power plus source.
19 TESIO0 I
Test input/output
20 P2VRREF - 2V REF by PLL only
21 SPDO O VCO sensor frequency shift
22 PDOS O output of phase error between EFM signal and PLC signal 72
23 PDO O output of phase error between EFM signal and PLCK signal 73
24 TMAXS O TMAX detection result output
25 TMAXS O TMAX detection result output
26 LPFN I
Inversion of low pass filter amplifier input
27 LPFO O Low pass filter amplifier output
28 PVREF - Dedication of PLL VREF
29 VCOREF I
VCO sensor frequency reference level
30 VCOF O VCO filter
31 AVSS - Analogue ground
32 SLCO O Data slice level generation "DAC" output
33 RFI I
RF signal input
34 AVDD - Analogue power source
35 RFCT I
RFRP signal sensor level input
36 RFZI I
RFRP zero cross input
37 RFRP I
Ripple
38 FEI I
Focus error signal input
39 SBAD I
Subbeam additional signal input
40 TSIN I
Test input
41 TEI I
Tracking error input
42 TEZI I
Tracking error zero cross input
43 FOO O Focus equaliser output
44 TRO O Tracking equaliser output
45 VREF - Analogue reference power
46 RFGC O RF magnitude regulation control output
47 TEBC O Tracking Blanca control signal output
48 FMO O Field equaliser output
49 FVO O Speed error signal or Field search "EQ" output
50 DMO O Disc equaliser output
IC904 MC74HC00AF(QUAD 2-INPUT NAND)
A1
1
B1
2
Y1
3
A2
4
B2
5
Y2
6
GND
7
No.
100
IC903 MC74HC175DR(QUAD D FLIP-FLOP)
V
14
CC
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
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Name I/O DESCRIPTION
51
2VREF - Analogue reference power
52
SEL O APC circuit on/off signal output
53
FLGA O External flag of internal signal monitor output
54
FLGB O External flag of internal signal monitor output
55
FLGC O External flag of internal signal monitor output
56
FKGD O External flag of internal signal monitor output
57
VDD - Digital pulse power source
58
VSS - Digital ground
59
IOO I/O General purpose I/O port
60
IO1 I/O General purpose I/O port
61
IO2 I/O General purpose I/O port
62
IO3 I/O General purpose I/O port
63
/DMOUT I Mode setting for IO0,1,2,3
64
/CKSE I X'tal select
65
/DACT I Test
66
TESIN I Test input
67
TESTIO1 I Test input/output
68
VSS - Digital ground
69
PXI I "DSP" clock oscillator input
70
PXO O "DSP" clock oscillator output
71
VDD - Digital pulse power source
XVSS - Ground for system clock oscillator
XI I System clock oscillator input
74
XO O System clock oscillator output
75
XVDD - System clock oscillator pulse power source
76
DVDD - power source for D/A converter
77
RO O "R" channel data output
78
DVSS - D/A converter analogue Ground
79
DVR - D/A converter Reference power source
80
LO O "L" channel data output
81
DVDD - D/A converter power source
82
TEST1 I Test port
83
TEST2 I Test port
84
TEST3 I Test port
85
BUSO I/O Data input for micon interface
86
BUS1 I/O Data input for micon interface
87
BUS2 I/O Data input for micon interface
88
BUS3 I/O Data input for micon interface
89
VDD - Digital power source
90
VSS - Digital ground
91
BUCK I Clock input for micon interface
92
/CCE I Chip enable signal input for micon interface
93
TEST4 I Test port
94
/TSMOD I Local test mode selector
95
/RST I Reset signal input
96
TEST0 I Test port
97
/HSO O Play speed mode flag output
98
/UHSO O Play speed mode flag output
99
EMPH O Subcode "Q" data emphasis flag output
LRCK O Channel clock(44.1kHz) output
VCC
1 16
Q3
2 15
Q3
3 14
D3
4 13
D2
5 12
Q2
6 11
Q2
7
10
CLOCK
8 9
Inputs Output
Reset Clock D Q Q
L X X L H
H H H L
H L L H
H L X
No Change