Foxconn P4M800P7MA series User Manual page 40

vDRAM Timing
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to "Auto By SPD" enables DRAM tim-
ings to be determined by BIOS based on the configurations on the SPD.
Selecting "Manual" allows users to configure the DRAM timings manually.
The setting values are:Manual, Auto By SPD, Turbo, Ultra.
vSDRAM CAS Latency [DDR/DDR2]
W hen synchronous SDRAM is installed, the number of clock cycles of CAS
latency depends on the SDRAM timing.
vBank Interleave
This field selects 2-bank or 4-bank interleave for the installed SDRAM. Dis-
able the function if 16MB SDRAM is installed.
vPrecharge to Active (Trp)
This option controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete
and DRAM may fail to retain data. This option applies only when synchro-
nous DRAM is installed in the system.
v Active to Precharge(Tras)
This option is used to set active to precharge(Tras).
v Active to CMD<Trcd>
W hen DRAM is refreshed, both rows and columns are addressed separately.
This setup option allows you to determine the timing of the transition from
RAS (row address strobe) to CAS (column address strobe). The less the
clock cycles, the faster the DRAM performance.
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DRAM Clock/Drive Control Menu
Chapter 3 BIOS Description