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3. IC901 (V Driver)
A V driver (IC901) is necessary in order to generate the clocks
(vertical transfer clock and electronic shutter clock) which
driver the CCD.
In addition the XV1-XV10 signals which are output from IC101
are vertical transfer clocks, and the XSG signal is superim-
posed onto XV1, XV3, XV5 and XV7 at IC901 in order to gen-
erate a ternary pulse. In addition, the XSUB signal which is
output from IC101 is used as the sweep pulse for the elec-
tronic shutter.
VMSUB
13
3-level
OSUB
14
9
VL
41
VL
2-level
OV1S
27
2-level
OV3L
25
2-level
OV3R
26
2-level
OV5L
23
2-level
OV5R
24
2-level
OV2
36
2-level
OV4
35
2-level
OV6
31
VM
12
VM
37
RESET
47
Level
SUBCNT
5
conversion
Level
6
SUB
conversion
VDC
7
Level
V6
46
conversion
Level
V4
45
conversion
Level
V2
44
conversion
Level
V5R
58
conversion
Level
V5L
59
conversion
Level
56
V3R
conversion
Level
V3L
57
conversion
Level
V1S
55
conversion
MODESEL
50
Fig. 1-3. IC901 Block Diagram
4. IC905 (H Driver, CDS, AGC and A/D converter)
IC905 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver and reset pulse for CCD
image sensor, H1, H2, H3, H4, HL and RG are generated
inside, and output to CCD.
The video signal which is output from the CCD is input to pin
(25) of IC905. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the VGA (VGA: Variable Gain Amplifier). It is con-
verted internally into a small-amplitude actuating signal
(LVDS), and is then input to IC101. The gain of the VGA am-
plifier is controlled by pins (32), (33) and (34) serial signals
which is output from IC101.
3-level
28 OV1C
3-level
29
OV1B
3-level
30 OV1A
3-level
20
OV3C
3-level
21 OV3B
3-level
22
OV3A
3-level
15
OV5C
3-level
18
OV5B
3-level
3V INPUT
19
OV5A
1.8V OUTPUT
10
VH
38
VH
8
GND
H1 TO H4
Level
64
CH9
conversion
Level
2
CH6
conversion
Level
3 CH3
conversion
Level
4
V5
conversion
Level
60
CH8
conversion
Level
61
CH5
conversion
Level
62
CH2
conversion
Level
63
V3
conversion
Level
51
CH7
conversion
Level
52
CH4
conversion
Level
53
CH1
conversion
Level
54 V1
conversion
– 4 –
REFT
6~42 dB
-3, 0, +3, +6dB
12-BIT
CDS
VGA
CCDIN
ADC
CLAMP
LDO
REG
INTERNAL
CLOCKS
RG
PRECISION
HORIZONTAL
HL
TIMING
DRIVERS
4
GENERATOR
SYNC
GENERATOR
HD
VD
GP01
GP02
Fig. 1-4. IC905 Block Diagram
REFB
AD9971
VREF
TCLKP
TCLKN
REDUCED
RANGE
DOUT0P
LVDS
DOUT0N
OUTPUT
DOUT1P
DOUT1N
SL
INTERNAL
SCK
REGISTERS
SDATA
CLI
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