Aiwa XR-MP50 Service Manual page 45

Pin No. Pin Name
27 PI8
28 XVDD
29 XVSS
30 SID
31 SII
32 SIC
33 PI4
34 PI3
35 PI2
36 PI1
37 PI0
38 CLKO
39 PUP
40 WSEN
41 WRDY
42 AVDD
43 CLKI
44 AVSS
I/O
I Start-up : clock output scaler on / off.
O Operation : MPEG CRC error.
– Positive supply of output buffers.
– Ground of output buffers.
I Serial input data. (Not used)
I Serial input frame identification. (Connected to VDD)
I Serial input clock. (Not used)
I Start-up : select SDI / PIO-DMA input mode.
O Operation : MPEG-frame Sync.
I Start-up : enable layer 3 / disable layer 3 decoding.
O Operation : MPEG header bit 20 (sampling frequency).
I Start-up : enable layer 2 / disable layer 2 decoding.
O Operation : MPEG header bit 21 (sampling frequency).
I Start-up : SDO: select 32-bit mode / 16-bit I
O Operation : MPEG header bit 30 (emphasis).
I Start-up : select multimedia mode / broadcast mode.
O Operation : MPEG header bit 31 (emphasis).
O Clock output for the D/A converter. (Not used)
O Power up, i.e. status of voltage supervision. (Not used)
I Enable DSP and start DC/DC converter.
If WSEN = 0: valid clock input at CLKI
O
If WSEN = 1: clock synthesizer PLL locked. (Not used)
– Supply for analog circuits.
I Clock input.
– Ground supply for analog circuits.
– 45 –
Description
2
S mode.