Sony STR-KS500 Service Manual page 30

STR-KS500
QQ
3 7 63 1515 0
DIGITAL BOARD IC1601 MB90488BPF-G-196E1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
1
DATAO
2
GP9
3 BST
4
HCS
5
HACN
6
XRST
7 PM
8
GP12
9
PCM1803_ RST
10
PCM1602_ RST
11 VSS
12
PCM1602_ ML
13
PCM1602_ MC
14
PCM1602_ MDI
15 PCM1602_ MDO
16
TUNER_CLK
17
TUNER_DATA
18
HDOUT
19 HDIN
20
HCLK
TE
21 L 13942296513
VOL_CLK
22
VOL_DATA
23 VCC5
24
ANA/DIG
25, 26
NOT IN USE
27, 28
FLASH2, FLASH1
29
SDA
30, 31
NO USE
32
NOT IN USE
33
SCL
34
NO USE
35 AVCC
36
AVRH
37
AVSS
38 to 40
A/D0 to A/D2
41 A/D3
42
VSS
43
RDS SIGNAL
44
MODEL
45 VERSION
46
FAN-HI-DETECT
www
47
NO USE
48
STOP
49 MD0
.
50
MD1
51
MD2
30
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I/O
I
Audio serial data input from the digital audio interface receiver
I
Read ready signal input from the audio digital signal processor
O Boot strap signal output to the audio digital signal processor
O
Chip select signal output to the audio digital signal processor
I
Acknowledge signal input from the audio digital signal processor
O
System reset signal output to the audio digital signal processor "L": reset
O PLL initialize signal output to the audio digital signal processor "L": initialize
O
Write signal output to the audio digital signal processor
O
System reset signal output to the A/D converter "L": reset
O
System reset signal output to the D/A converter "L": reset
- Ground terminal
O
Serial data latch pulse signal output to the D/A converter
O
Serial data transfer clock signal output to the D/A converter
O
Serial data output to the D/A converter
I Serial data input from the D/A converter
O
Serial data transfer clock signal output to the tuner
O
Serial data output to the tuner
I
Serial data input from the audio digital signal processor
O Serial data output to the audio digital signal processor
O
Serial data transfer clock signal output to the audio digital signal processor
O
Serial data transfer clock signal output to the electrical volume
O
Serial data output to the electrical volume
- Power supply terminal (+3.3V)
O
Analog/digital selection signal output terminal Not used
O
Not used
O
Flash programming signal output terminal
I/O
Two-way data bus with the EEPROM
O
Not used
O
Not used
O
Serial data transfer clock signal output to the EEPROM
O
Not used
- Power supply terminal (+3.3V)
I
Reference voltage (+3.3V) input terminal
-
Ground terminal
I
Front panel key input terminal (A/D input)
I Key input terminal Not used
-
Ground terminal
I
RDS signal input from the tuner
I
Setting terminal for the model (A/D input)
I Setting terminal for the destination (A/D input)
I
Fan motor hi-speed detection signal input terminal
O
Not used
x ao u163
I
AC off detection signal input terminal "L": AC off
y
I CPU operation mode setting signal input terminal
i
I
Setting terminal for the CPU operation mode Fixed at "H" in this set
I
CPU operation mode setting signal input terminal
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2 9
8
Description
Q Q
3 6 7 1 3 1 5
co
.
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9