Pll Ic (Ic502); Local Switch (D600, D601) - Kenwood NX-300 Service Manual

NX-300

5-3. PLL IC (IC502)

The PLL IC compares the differences in phases of the
VCO oscillation frequency and the VCTCXO reference fre-
quency, returns the difference to the VCO CV terminal and
realizes the "Phase Locked Loop" for the return control.
This allows the VCO oscillation frequency to accurately
match (lock) the desired frequency.
When the frequency is controlled by the PLL, the fre-
quency convergence time increases as the frequency differ-
ence increases when the set frequency is changed. To sup-
plement this, the ASIC is used before control by the PLL IC
to bring the VCO oscillation frequency close to the desired
frequency. As a result, the VCO CV voltage does not change
and is always stable at approximately 2.5V.
X500
19.2MHz
VC
TCXO
SDO1
SCK1
/PCS_RF
6. Control Circuit
The control circuit consists of the ASIC (IC108) and its
peripheral circuits. IC108 mainly performs the following;
1) Switching between transmission and reception by PTT
signal input.
2) Reading system, zone, frequency, and program data
from the memory circuit.
3) Sending frequency program data to the PLL.
4) Controlling squelch on/off by the DC voltage from the
squelch circuit.
5) Controlling the audio mute circuit by decode data input.
14
CIRCUIT DESCRIPTION
Q508,Q509
D506,D507,D510,D511
D514~D517,D519
IC502
PLL Loop
VCO
IC Filter
Q504
CV
VCO_MOD
IC504(1/2)
150C
Q503
Ripple
Filter
IC503
ASSIST
Fig. 7 PLL block diagram
The desired frequency is set for the PLL IC by the ASIC
(IC108) through the 3-line "SDO1", "SCK1", "/PCS_RF"
serial bus. Whether the PLL IC is locked or not is monitored
by the ASIC through the "PLD" signal line. If the VCO is not
the desired frequency (unlock), the "PLD" logic is low.

5-4. Local Switch (D600, D601)

The connection destination of the signal output from the
buffer amplifier (Q600) is changed with the diode switch
(D601) that is controlled by the transmission power supply,
50T, and the diode switch (D600) that is controlled by the
receive power supply, 50R. If the 50T logic is high, it is con-
nected to a send-side pre-drive (Q601). If the 50T logic is
low, it is connected to a receive-side mixer (Q703).
Q512 Q600 D600,D601
BUFF BUFF T/R
AMP AMP SW
50C
LPF
6-1. ASIC
The ASIC (IC108) is a 32-bit RISC processor, equipped
with peripheral function and ADC/DAC.
This ASIC operates at 18.432MHz clock and 3.3V /1.5V
DC. It controls the fl ash memory, SRAM, DSP, the receive
circuit, the transmitter circuit, the control circuit, and the dis-
play circuit and transfers data to or from an external device.
to TX stage