Yamaha DSP-AX2700 Service Manual page 125

A B C
NET 1/3
1
NET
11.8
11.8
11.7 1.7
3.3 3.3
RESET CIRCUIT
3.3
2
3.3
3.3
3.3
3.3 0
3.3 0
0 0
0
0
3.3 3.2
0
3.3 3.3
3
0 0
3.3
0.1
3.3 0 3.3 0
3.3 3.3 3.3 3.3
0 0
3.3 3.3
4
REGULATOR
3.3 1.8
A-3
5
0.8
0.9
1.8
0
Page 112 F8
to FUNCTION (1)_CB408
6
5.0 3.3
5.0 3.3
5.0 3.3
7
8
IC613: S29JL032H70TFI020
32M bit cmos 3.0V simple power read/write simultaneously executed flash memory
9 V
CC OE# BYTE#
V
SS
Mux
Bank 1
A20-A0 Bank 1 address
X-decoder
RY/BY# Bank 2 address Bank 2
X-decoder
A20-A0
State control
RESET#
WE#
DQ15-DQ0
CE# Command
resister
BYTE#
Mux
10 WP#/ACC
DQ0-DQ15
X-decoder
Bank 3
Bank 3 address
X-decoder
A20-A0
Bank 4 address
Bank 4
Mux
D E F
~ 0
~ 0
3.3
3.3
3.3
0
3.3
3.3
0.1
B-1
0
0
MICROPROCESSOR
0.8
0.8
(NET)
1.8
1.9
0
3.3
3.3
3.2
3.3
0
1.8
0
3.3
3.3
0.9
0
1.7
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
0
3.3
3.3
3.3
3.3
3.3
POWER DISTRIBUTION
5.0
3.3
3.3 5.0
0
5.0
Page 116
to OPERATION (7)_CB814
IC611: EDS1216AATA-75-E
128M bit SDRAM
CLK 38
Clock
Generator
CKE 37
A15 1 48 A16
A14 2 47 BYTE# Address
V
A13 3 46 SS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
Mode
A10 6 43 DQ14
Register
A9 7 42 DQ6
A8 8 41 DQ13
A19 9 40 DQ5
A20 10 39 DQ12
WE# 11 38 DQ4
RESET# 12 37 V
CC /CAS 19
NC 13 36 DQ11
WP#/ACC 14 35 DQ3
/RAS 18
RY/BY# 15 34 DQ10
A18 16 33 DQ2
/CS 17
A17 17 32 DQ9
A7 18 31 DQ1
/WE 16
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 V
SS
A2 23 26 CE#
A1 24 25 A0
G H I
POINT A-3 Pin 2 of IC605 POINT B-1 Pin 118 of IC610
3.3
1.2
3.3
0.2
0.1
0
0 0.1
0.1
3.3
3.3
0.1
0.2 0.1
0.1 1.3
0.1 0
0.1 0.2
0.7 3.3
0 3.3
3.3
3.3
0.1 3.3
3.3
0.1
0.1 3.3
0.1 0.1
0.1 0.1
0 0.1
0.1
1.9
0.2 0.1
0.1 0.1
0.1 0.1
0.1 3.3
0.1
0
3.3
0.1
3.3
3.3
3.3
3.3
0
3.3
3.3
3.3
0
1.9
1.6
0
3.3
3.1
3.3
3.1
1.7
3.1
0
3.1
0
3.1
0
0
0.3
0
LOGIC FOR AUDIO CLOCK
Page 110 J1
to DSP_CB531
J5
1 54
VDD VSS
2 53
DQ0 DQ15
VDDQ 3 52 VSSQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
Bank 3
6 49
VSSQ VSSQ
Bank 2
7 48
DQ3 DQ12
8 47
Bank 1 DQ4 DQ11
Row VDDQ 9 46 VSSQ
Address DQ5 10 45 DQ10
Buffer DQ6 11 44 DQ9
&
12 43
VSSQ VSSQ
Refresh
Bank 0 13 42
Counter DQ7 DQ8
14 41
VDDD VSS
LDQM 15 40 NC
16 39
/WE UDQM
15 UDQM 17 38
Sense Amplifier /CAS CLK
and
39 LDQM /RAS 18 37 CKE
Column Decoder &
Column /CS 19 36 NC
Latch Circuit
Address 20 35
BA0 A11
Buffer
21 34
BA1 A9
&
22 33
A10 A8
Burst
Data Control Circuit DQ
Counter A0 23 32 A7
A1 24 31 A6
25 30
A2 A5
26 29
A3 A4
27 28
VDD VSS
J K L
IC617: SN74LV74APWR
Dual positive edge triggerd D-type flip flop
1CLR 1 14 Vcc
1D 2 13 2CLR
1CLK 3 12 2D
1PRE 4 11 2CLK
1Q 5 10 2PRE
1Q 6 9 2Q
GND 7 8 2Q
SDRAM
FLASH
128Mbit
32Mbit
0
0
0.2
0.1 0.1
0
3.3
0.1
0.1
0.1 0
0.2
0.1 0.2
3.3
0.1 0.2
0.1
0.1 0.1
0.1
0.1 1.3
0
0.1 0.2
0.7
0.1
0.1
0.1
3.3 0.1
3.3
3.3 3.3
0.2
0.1
0 3.3
0.1
3.3
0.7
0.1 0.1
1.6
0.1 0.1
3.3
0.4 0.2
0.1 0.2
0.1
0.1 1.2
0.1
0.1 3.3
0.1
0.1 0
0.1
0.1 3.3
0.1
0.1 0.1
0.1
0.1
0
No replacement part available.
3.3 3.3 3.3
3.3
3.3
0.3
1.7 1.7 0.1
0 1.7 0.1
0 3.3 0.1
2.2 0 1.7 3.3
0 1.7 1.7 0.1
3.3
0
0.3 0.3 3.3
3.3 0
3.3
LOAD
ENT
To NET 3/3 ENP
CLK
CLR
To NET 2/3
IC614: 74LCX07MTCX
Low voltage hex buffer with open drain outputs
A0 1
IC610: EP9301-CQZ O0 2
System on chip processor A1 3
O1 4
A2 5
Serial O2 6
Audio
Interfacce Peripheral Bus GND 7
Clocks &
Timers
12 Channel DMA
(2) UARTs ARM920T
w/
Interrupts
# All voltages are measured with a 10MΩ/V DC electronic voltmeter.
IrDA
D-Cache I-Cache & GPIO
# Components having special characteristics are marked s and must be replaced
16KB 16KB
MaverickKey TM
(2) USB
MMU
# Schematic diagram is subject to change without notice.
Hosts Bus Bridge
Processor Bus
Ethernet Boot SRAM & Unified
MAC
ROM Flash I/F SDRAM I/F
MEMORY AND STORAGE
M N
RX-V2700/DSP-AX2700
IC601: BD4830FVE-TR
IC602 : SN74LVC14APWR
Voltage detector IC
Hex schmitt trigger inverter
V
DD
5 1A 1 14 VCC
1Y 2 13 6A
Vout
1
2A 3 12 6Y
– 2Y 4 11 5A
+
3A 5 10 5Y
Vref
3Y 6 9 4A
SUB
2
GND 7 8 4Y
4 3
GND N.C.
IC604: PQ018EZ01ZP IC605: SN74LVC1GU04DCKR
Voltage regulator Single inverter
DC input DC output
1 3
(Vin) (Vo) NC 1 5 V
CC
A 2
IC
GND 3 4 Y
ON/OFF control
2
(Vc)
5
GND
IC609: MIC2026-2BM
Dual channel power distribution switch
2 FLGA
FLAG
RESPONSE
8 OUTA
DELAY
ENA 1
CHARGE
GATE
PUMP
CONTROL
CURRENT
LIMIT
THERMAL THERMAL 1.2V
OSC. 7 IN
SHUTDOWN SHUTDOWN REFERENCE
CHARGE
CURRENT
PUMP
LIMIT
GATE
CONTROL
ENB 4
FLAG 5 OUTB
RESPONSE
DELAY
3 FLGB
6
GND
ENA 1 8 OUTA
FLGA 2 7 IN
FLGB 3 6
GND
ENB 4 5 OUTB
IC615, 616: SN74LV163APWR
4 bit synchronous binary counters
9
10
RCO
15
LD
7
CK
2
CK LD
1
R
M1
G2
1,2T/1C3
14 QA
G4
A 3 3D
4R
M1
G2
1,2T/1C3
13 QB
G4
B 4 3D
4R
M1
G2
1,2T/1C3
12 QC
G4
C 5
3D
4R
M1
G2
1,2T/1C3
11 QD
G4
D 6 3D
4R
CLR 1 16 VCC
CLK 2 15 ROC
A 3 14 QA
B 4 13
QB
C 5 12 QC
D 6 11 QD
7 10 ENT
ENP
GND 8 9 LOAD
14 VCC
13 A3
12 O3
11 A4
10
O4
9 A5
8 O5
with parts having specifications equal to those originally installed.
125