Sony CDX-C4750 Service Manual page 21

4-3. CIRCUIT BOARDS LOCATION
DISC IN SW board
tuner assy
(TU601)
DISPLAY board
LOAD SW board
– 23 –
SUB board
LIMIT SW board
MAIN board
SERVO board
THIS NOTE IS COMMON FOR PRINTED WIRING
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is
printed in each block.)
for schematic diagram:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ω and
1 / W or less unless otherwise
4
specified.
• % : indicates tolerance.
• : internal component.
¢
• C : panel designation.
Note: The components identified by mark ! or dotted line
with mark ! are critical for safety.
Replace only with part number specified.
• U : B+ Line.
• Power voltage is dc 14.4V and fed with regulated dc power
supply from ACC and BATT cords.
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
F : FM
f : AM
J : CD
for printed wiring boards:
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
• : Through hole.
®
• b : Pattern from the side which enables seeing.
(The other layer's patterns are not indicated.)
Caution:
Pattern face side: Parts on the pattern face side seen from the
(Side B) pattern face are indicated.
Parts face side: Parts on the parts face side seen from the
(Side A) parts face are indicated.
• Waveforms (MODE:PLAY)
1
Approx. 620mVp-p
1
IC2 (FEO)
2
#¡
IC2 (RFO)
3
Approx. 200mVp-p
$™
IC2 (TEO)
4
2.6Vp-p
7.6µsec
3
(MDP)
IC1
5
5.8Vp-p
22.7µsec
@º
(LRCK)
IC1
6
474nsec
@™
(BCK)
IC1
7
3.2Vp-p
16.89MHz
#¢
IC1 (XTAI)
– 24 –
0V
1.2Vp-p
0V
5.7Vp-p