Pcm1791 Terminal Function - Denon AVR-3803 Service Manual

Av surround receiver/amplifier
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PCM1791 (AD: IC523~526)

PCM1791 Terminal Function

Pin
Pin Name
No.
1
LRCK
TE
L 13942296513
2
BCK
3
DATA
4
MUTE
5
SCKI
6
RST
7
V
DD
8
DGND
9
AGNDF
10
V
R
CC
11
AGNDR
12
V
R-
OUT
13
V
R+
OUT
14
V
COM
15
V
C
CC
16
AGNDC
17
V
L+
OUT
18
V
L-
OUT
19
AGNDL
20
V
L
CC
21
V
F
CC
22
ZEROR
23
ZEROL
www
24
RSV
25
MDO
26
MDI
27
MC
.
28
MS
*
Schmitt trigger input, 5V tolerant.
** Tristate output.
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L R C K
1
B C K
2
D ATA
3
M U T E
4
S C K I
5
R S T
6
V
7
D D
D G N D
8
A G N D F
9
V
R
1 0
C C
A G N D R
1 1
V
R -
1 2
O U T
V
R +
1 3
O U T
V
1 4
C O M
I/O
Left and right clock (f
I
Connected to GND in DSD mode*
I
Bit clock input. Connected GND for DSD mode*
Serial audio data input for normal operation. L-channel audio data input for external DF and DSD
I
modes*
Analog output mute control for normal operation. R-channel audio data input for external DF and
I
DSD modes*
I
System Clock Input. BCK (64f
I
Reset*
Digital power supply, +3.3 V
Digital ground
Analog ground (DACFF)
Analog power supply (R-channel DAC), +5.0 V
Analog ground (R-channel DAC)
O
R-channel analog voltage output-
O
R-channel analog voltage output+
Internal bias de-coupling pin
Analog power supply (internal bias), +5.0 V
Analog ground (internal bias)
O
L-channel analog voltage output+
O
L-channel analog voltage output-
Analog ground (L-channel DAC)
Analog power supply (L-channel DAC), +5.0 V
Analog power supply ( DACFF), +5.0 V
O
Zero flag for R-channel
O
Zero flag for L-channel
Reserved pin. It must be open.
O
Serial data output for function control register**
x
ao
u163
y
I
Serial data input for function control register*
I
Shift clock for function control register*
i
I
Mode control chip select and latch signal*
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2 9
8
T O P V I E W
2 8
M S
2 7
M C
2 6
M D I
2 5
M D O
2 4
R S V
2 3
Z E R O L
2 2
Z E R O R
2 1
V
F
C C
2 0
V
L
C C
1 9
A G N D L
1 8
V
L-
O U T
1 7
V
L +
O U T
A G N D C
1 6
1 5
V
C
C C
DESCRIPTIONS
) input for normal operation. WDCK clock input in external DF mode.
s
Q Q
3
6 7
1 3
) clock input for DSD mode*
s
.
AVR-3803/1083/AVC-3570
9 4
2 8
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9
31

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