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IC BLOCK DIAGRAM
Q701:LM7001J
6
SYC
2
X IN
1
XOUT
11
FM IN
10
AM IN
Pin No. Terminal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Programable Divider
Shift Register/Latch
3
4
5
CE
CL
DATA
Description
XOUT
Connect the 7.2MHz crystal resonator.
XIN
CE
Chip enable terminal.Connect to the terminal PLL of microprocessor.
CL
Serial clock input terminal.Connect to the terminal CLK of microprocessor.
DATA
Serial clock input terminal.Connect to the terminal DATA of microprocessor.
SNY
Not used.
BO1
Auto/Mono control terminal.
BAND1
Band selector output terminal.Low level at FM.
BAND2
Band selector output terminal.Low level at AM.
AMIN
AM local oscillator input terminal.
FMIN
FM local oscillator input terminal.
VDD1
Power souce terminal for back-up.
VDD2
Power souce terminal .
PD1
Phase comparator output terminal.
PD2
Phase comparator output terminal.
VSS
Ground terminal
Reference Divider
7
8
BO1
BO2
Phase
Detector
Charge Pump
9
BO3
T-405TX
14
PD1
15
PD2
12
VDD1
13
VDD2
16
VSS
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