Yamaha RX-V671 Service Manual page 73

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Pin
Port Name
Function Name
No.
IIO1_0/TXD8/N_SS2/
42
N_RTS2/N_CTS2/V/
DK1_N_IPDET
TA1IN/P7_3
CLK2/V/TA1OUT/
43
SR_PON
P7_2
MSCL/IEIN/ISRXD2/
OUTC2_2/IIO1_7/
44
SR_MISO
STXD2/SCL2/RXD2/
TA0IN/TB5IN/P7_1
TA0OUT/TXD2/
SDA2/SRXD2/
45
IIO1_6/OUTC2_0/
SR_MOSI
ISTXD2/IEOUT/
MSDA/P7_0
TXD1/SDA1/SRXD1/
46
232C_DBG_MOSI
P6_7
47 P14_7
DSP_PON
RXD1/SCL1/STXD1/
48
232C_DBG_MISO
P6_6
49 P11_7
DAC_N_CS
50 CLK1/P6_5
DBG_SCK
N_CTS1/N_RTS1/
51
N_SS1/OUTC2_1/
DBG_BUSY
ISCLK2/P6_4
TXD0/SDA0/SRXD0/
52
DSP_MOSI
P6_3
TB2IN/RXD0/SCL0/
53
DSP_MISO
STXD0/P6_2
54 TB1IN/CLK0/P6_1
DSP_SCK
TB0IN/N_CTS0/N_
55
NCPU_N_INT
RTS0/N_SS0/P6_0
56 P19_5
D31/OUTC2_7/
57
DSP1_N_RST
P13_7
D30/OUTC2_1/
58
EX_SCK
ISCLK2/P13_6
D29/OUTC2_2/IS-
59
EEP_MISO
RXD2/IEIN/P13_5
D28/OUTC2_0/
60
ISTXD2/IEOUT/
EX_MOSI
P13_4
61 P19_4
EEP_N_CS
RDY/CS3/N_CTS7/
62
FPGA_N_CS
N_RTS7/P5_7
63 ALE/CS2/RXD7/P5_6 DFF2_N_CS
64 HOLD/CLK7/P5_5
DBG_EPM
HLDA/CS1/TXD7/
65
DFF1_N_CS
P5_4
D27/OUTC2_3/
66
P13_3
67 VSS
VSS
D26/OUTC2_6/
68
DSP1_N_SPIRDY
P13_2
69 VCC
VCC
D25/OUTC2_5/
70
DSP2_N_CS
P13_1
D24/OUTC2_4/
71
DSP1_N_CS
P13_0
72 CLKOUT/BCLK/P5_3 NC(BCLK)
73 RD/P5_2
MCBUS_N_RD
74 WR1/BC1/P5_1
NC(BC1)
MCBUS_N_WR
75 WR0/WR/P5_0
DBG_N_CE
76 D23/P12_7
MT_DA
77 D22/P12_6
DIR_N_CS
78 D21/P12_5
DIR_N_RST
Related Power Supply
ON
OFF
I/O
Logic
I/O
Logic
I
L act
O
Low
O
H act
O
Low
I
Data
O
Low
O
Data
O
Low
O
Data
O
Low
O
H act
O
Low
I
Data
O
Low
O
L act
O
Low
I
Clock
O
Low
O
O
Low
O
Data
O
Low
I
Data
I
O
Clock
O
Low
I
H act
O
Low
---
I
---
I
O
L act
O
Low
O
Clock
O
Low
I
Data
O
Low
O
Data
O
Low
O
L act
O
Low
B
Bus
O
Low
B
Bus
O
Low
I
I
B
Bus
O
Low
---
O
Low
O
Low
I
L act
O
Low
O
L act
O
Low
O
L act
O
Low
B
Bus
O
Low
B
Bus
O
Low
B
Bus
O
Low
B
Bus
I
I
I
O
H act
O
Low
O
L act
O
Low
O
L act
O
Low
Detail of Function
Dock iPod detect
SIRIUS power supply control
SIRIUS reception data
SIRIUS transmission data
RS-232C transmission data / Debug / E8a
DSP power supply
RS-232C reception data / Debug / E8a
DAC chip select (SW of V3071, FP DAC is D-FF)
E8a
E8a
DSP/DIR/DAC transmission data
---
DSP/DIR/DAC reception data
DSP/DIR/DAC communication clock
Network microprocessor interrupt
---
No used (+3.3DSP is applied, input port setting)
DSP1 reset
FL/EEPROM/ expansion IO communication clock
EEPROM reception data
FL/EEPROM/ expansion IO transmission data
EEPROM chip select
External bus FPGA chip select
External bus DFF2 chip select
---
E8a
External bus DFF1 chip select
No used
---
DSP1 SPI ready
---
DSP2 chip select
DSP1 chip select
External bus
External bus
External bus
---
External bus
---
E8a
Mute Digital Audio
DIR chip select
DIR reset
RX-V671/HTR-6064/RX-A710
73

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