Sharp LC-39LE650E Service Manual page 53

MAJOR ICs INFORMATION ( continued )
IC 3800: STANDBY CONTROLLER
Part number: STM8S105K4T6CTR (ST MICRO)
Sharp code: RH-IXD550WJZZY
http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00200092.pdf
Features
Core.
16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline.
o
Extended instruction set.
o
Memories.
Medium-density Flash/EEPROM:
o
ƒ Program memory up to 32 Kbytes (data retention: 20 years at 55°C after 10k cycles).
ƒ
Data memory up to 1 Kbytes true data EEPROM (endurance 300k cycles).
RAM: Up to 2 Kbytes.
o
Clock, reset and supply management.
2.95 V to 5.5 V operating voltage.
o
Flexible clock control, 4 master clock sources:
o
ƒ Low power crystal resonator oscillator.
ƒ
External clock input.
ƒ Internal, user-trimmable 16 MHz RC.
ƒ
Internal low power 128 kHz RC.
Clock security system with clock monitor.
Power management:
Low power modes (wait, active-halt, halt).
o
Switch-off peripheral clocks individually.
o
Permanently active, low consumption power-on and
power-down reset.
Interrupt management
Nested interrupt controller with 32 interrupts.
o
Up to 37 external interrupt on 6 vectors.
o
Timers.
2x 16-bit general purpose timers, with 2+3
o
CAPCOM channels (IC, OC or PWM).
Advanced control timer: 16-bit, 4 CAPCOM
o
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization.
8-bit basic timer with 8-bit prescaler.
o
Auto wake-up timer.
o
Window and independent watchdog timers.
o
Communications interfaces.
UART with clock output for synchronous
o
operation, Smartcard, IrDA, LIN.
SPI interface up to 8 Mbit/s.
o
I2C interface up to 400 Kbit/s.
o
Analog-to-digital converter (ADC).
10-bit, ±1 LSB ADC with up to 10
o
multiplexed channels, scan mode and analog
watchdog.
I/Os.
Up to 38 I/Os on a 48-pin package including
o
16 high sink outputs.
Highly robust I/O design, immune against
o
current injection
Unique ID.
96-bit unique key for each device.
o
53
LC-39/50LE650
LC-39/50LE651
LC-39/50LE652