LG 55LM8600 Service Manual page 21

System Configuration
Clock for LG1152
MAIN Clock(24Mhz)
XIN_MAIN
XO_MAIN
PLL SET[1:0] ==> Internal Pull-UP. N.C is high
00 : CPU clock(1056Mhz), Main0,1/2 DDR (792/792 Mhz)
01 : CPU clock(792Mhz), Main0,1/2 DDR (672/792 Mhz)
10 : CPU clock(1152Mhz), Main0,1/2 DDR (792/672 Mhz)
11 : CPU clock(984Mhz), Main0,1/2 DDR (792/792 Mhz)
OPT
R102 22
PLLSET1
R103 22
PLLSET0
OPT
BOOT MODE
"11" or "01" : NOR
"10" : eMMC
JTAG I/F FOR MAIN
"00" : NAND
+3.3V_NORMAL
+3.3V_NORMAL
BOOT_MODE1
TRST_N0
BOOT_MODE1
TDI0
TDO0
+3.3V_NORMAL TMS0
TCK0
SOC_RESET
BOOT_MODE0
BOOT_MODE0
+3.3V_NORMAL
HW_OPT_0
BackEnd 1
HW_OPT_1
BackEnd 2
HW_OPT_2
Pannel Resol
HW_OPT_3
OPTIC I/F
HW_OPT_4
3D Depth IC
HW_OPT_5
DDR Size
HW_OPT_6
CP BOX
HW_OPT_7
FrontEnd 1
HW_OPT_8
FrontEnd 2
HW_OPT_9
HW_OPT_10
OPT
22
HP_AMP_MUTE
R117
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2012 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3V_NORMAL
NVRAM
C111
0.1uF
IC102
R1EX24256BSAS0A
Write Protection
A0 VCC
1 8
- Low : Normal Operation
A1 WP - High : Write Protection
2 7
A2 A0'h SCL
3 6 I2C_SCL5
VSS SDA
4 5 I2C_SDA5
R142
OPT
R143 22
I2C_SCL3
OPT 22
I2C_SDA3
Place to LVDS Wafer
R151 22
FRC_RESET FRC3_RESET
3D_DEPTH_RESET
R160 22
I2C_SDA1 I2C_BE_SDA1
R162 22
I2C_SCL1 I2C_BE_SCL1
LOCAL_DIM_EN
+3.3V_NORMAL
+5V_NORMAL
SOC_RX
Q100
2N7002K
SOC_TX
Q103
2N7002K
+5V_NORMAL
+3.3V_NORMAL
MHL_DET
Q105
2N7002K OPT
HDMI_INT
SoC
NO_FRC internal LG FRC3 URSA5
FRC
MODEL_OPT_0
0 0 1 1
MODEL_OPT_1
0 1 0 1
HIGH LOW
MODEL_OPT_2 FHD UD
MODEL_OPT_3 OPTIC NON_OPTIC
3D DEPTH 3D_Depth_IC
MODEL_OPT_4 NON_3D_Depth_IC
DDR Reserved DDR_Default
MODEL_OPT_5
MODEL_OPT_6 CP BOX Enable Disable
MODEL_OPT_7
T2 Tuner Support Not Support
+3.3V_NORMAL
MODEL_OPT_8 I2C PULL UP
S Tuner Support Not Support
Support
MODEL_OPT_9 C2 Tuner Not Support
MODEL_OPT_10 Zoran FRC Support
Not Support
(For UD)
MODEL OPTION 8 is just for CP Box
It should not be appiled at MP
for DiiVA(China)
EB_ADDR[0-14]
A22
XIN_MAIN XIN_MAIN
B22
R104 560
XO_MAIN
1% XO_MAIN
AB16
OPM1
AB17
OPM0
AE3
SOC_RESET PORES_N
V23
TRST_N0 TRST_N0
U25
TMS0
TMS0
V25
TCK0 TCK0
V24
TDI0
TDI0
U24
TDO0 TDO0
Y22
TRST_N1
AA22
TMS1
AB20
TCK1
AB21
TDI1
W22
TDO1
AB9
PLLSET1 PLLSET1
AB8
PLLSET0 PLLSET0
BOOT_MODE1
AB15
BOOT_MODE1
BOOT_MODE1
BOOT_MODE0
AB14
BOOT_MODE0 BOOT_MODE0
Y23
R150 22
ERROR_OUT EXT_INTR3/GPIO48
W25
EPHY_INT
EXT_INTR2/GPIO63
W24
R101 22
/USB_OCD2 EXT_INTR1/GPIO62
W23
/USB_OCD3
EXT_INTR0/GPIO61 LG1152D-B1
Y5
UART0_RX/GPIO49
W6
LG1152_NON_RM
UART0_TX/GPIO50
AA6
UART1_RX UART1_RX
Y6
UART1_TX
UART1_TX
AB5
M_REMOTE_RX UART2_RX
AA5
M_REMOTE_TX
UART2_TX
AB23
IRB_SPI_MISO
SPI_DI0/GPIO39
AB24
IRB_SPI_MOSI SPI_DO0/GPIO38
AA25
IRB_SPI_CK
SPI_SCLK0/GPIO37
AB25
IRB_SPI_SS SPI_CS0/GPIO36
Y25
AV1_CVBS_DET SPI_DI1/GPIO35
AA23
SPI_DO1/GPIO34
Y24
SPI_SCLK1/GPIO33
DTV_ATV_SELECT
AA24
SPI_CS1/GPIO32
AB6
I2C_SCL1
SCL0/GPIO60
AB4
I2C_SDA1 SDA0/GPIO59
AC5
I2C_SCL2
SCL1/GPIO58
AC4
I2C_SDA2 SDA1/GPIO57
AD4
I2C_SCL3
SCL2/GPIO56
AE4
I2C_SDA3 SDA2/GPIO71
AE5
I2C_SCL4
SCL3/GPIO70
AD5
I2C_SDA4 SDA3/GPIO69
AE6
I2C_SCL5 SCL4/GPIO68
AD6
I2C_SDA5 SDA4/GPIO67
AC6
I2C_SCL6 SCL5/GPIO66
AC7
I2C_SDA6 SDA5/GPIO65
I2C_SDA1
I2C_SCL1
I2C_SDA2
I2C_SCL2
I2C_SDA3
I2C_SCL3
+3.3V_NORMAL
I2C_SDA4
I2C_SCL4
I2C_SDA5
I2C_SCL5
I2C_SDA6
I2C_SCL6
HP_DET
EPHY_INT
SEL_USB1
SEL_USB2
SEL_USB3
/RST_PHY
SC_DET
DiiVA_POD_CTL
EB_DATA[0-7]
+3.3V_NORMAL
E28
EMMC_RST
F27
EMMC_CLK
F26
EMMC_CMD
C26 EMMC_DATA[7]
EMMC_DATA7
E27
EMMC_DATA[6]
EMMC_DATA6
E26 EMMC_DATA[5]
EMMC_DATA5
D27
EMMC_DATA[4]
EMMC_DATA4
D28 EMMC_DATA[3]
EMMC_DATA3
C27
EMMC_DATA[2]
EMMC_DATA2
C28 EMMC_DATA[1]
EMMC_DATA1
D26
EMMC_DATA[0]
EMMC_DATA0
R23
NAND_CS1
P24
NAND_CS0
N25
NAND_ALE
P23
NAND_CLE
N24
NAND_REN
P25
NAND_WEN
AC1
GPIO31
V7
GPIO30
W5
GPIO29
W4
GPIO28
V6
IC100 GPIO27
V5
GPIO26
V4
GPIO25
U6
GPIO24
U5
GPIO23
U4
GPIO22
T6
GPIO21
T5
GPIO20
T4
GPIO19
R6
GPIO18
R5
GPIO17
R4
GPIO16
P6
GPIO15
P5
GPIO14
P4
GPIO13
N6
GPIO12
N5
GPIO11
N4
GPIO10
N3
GPIO9
M6
GPIO8
AC23
GPIO7
AC24
GPIO6
AE24
GPIO5
AD23
GPIO4
AE23
GPIO3
AC22
GPIO2
AD22
GPIO1
AE22
GPIO0
RCLAMP0502BA
Place near Jack side
LG1152 B1
MAIN & GPIO
I2C_SDA2
I2C_SCL2
SMARTCARD_DATA
SMARTCARD_RST
SMARTCARD_PWR_SEL
SMARTCARD_VCC
SMARTCARD_DET
SMARTCARD_CLK
MOTOR_CLOSE_SW
MOTOR_OPEN_SW
A22 E28
B22 XIN_MAIN EMMC_RST F27
AB16 XO_MAIN EMMC_CLK F26
AB17 OPM1 EMMC_CMD C26
OPM0 EMMC_DATA7 E27 MOTOR_CW
AE3 PORES_N EMMC_DATA6 EMMC_DATA5 E26
EMMC_DATA4 D27
V23 TRST_N0 EMMC_DATA3 D28
V25 U25 TMS0 EMMC_DATA2 C28 C27
V24 TCK0 EMMC_DATA1 D26 MOTOR_CCW
U24 TDI0 EMMC_DATA0
Y22 TDO0 R23
AA22 TRST_N1 NAND_CS1 P24
AB20 TCK1 TMS1 NAND_CS0 NAND_ALE N25 MO_SENS_TO_MAIN_UP
AB21 TDI1 NAND_CLE P23
W22 TDO1 NAND_REN N24
AB9 PLLSET1 NAND_WEN P25
AB15 AB8 PLLSET0 AC1 MO_SENS_TO_MAIN_DOWN
AB14 BOOT_MODE1 GPIO31 V7
BOOT_MODE0 GPIO30 W5
Y23 GPIO29 W4
W25 EXT_INTR2/GPIO63 EXT_INTR3/GPIO48 GPIO27 GPIO28 V6
W24 EXT_INTR1/GPIO62 GPIO26 V5
W23 EXT_INTR0/GPIO61 GPIO25 V4
GPIO24 U6
W6 Y5 UART0_RX/GPIO49 GPIO23 U4 U5
AA6 UART0_TX/GPIO50 GPIO22 T6
Y6 UART1_RX GPIO21 T5
AB5 UART1_TX GPIO20 T4
AA5 UART2_RX GPIO19 R6
UART2_TX GPIO18 GPIO17 R5 OPTIC_FPGA_RESET
AB23 SPI_DI0/GPIO39 GPIO16 R4
AB24 SPI_DO0/GPIO38 GPIO15 P6
AA25 AB25 SPI_SCLK0/GPIO37 GPIO14 P5 P4
Y25 SPI_CS0/GPIO36 GPIO13 N6
AA23 SPI_DI1/GPIO35 GPIO12 N5 OPTIC_SERDES_RESET
Y24 SPI_DO1/GPIO34 GPIO11 N4
AA24 SPI_SCLK1/GPIO33 GPIO10 N3
SPI_CS1/GPIO32 GPIO9 GPIO8 M6
AB6 SCL0/GPIO60 GPIO7 AC23 OLED_TCON_RESET
AB4 SDA0/GPIO59 GPIO6 AC24
AC4 AC5 SCL1/GPIO58 GPIO5 AE24 AD23
AD4 SDA1/GPIO57 GPIO4 AE23
AE4 SCL2/GPIO56 GPIO3 AC22
AE5 SDA2/GPIO71 GPIO2 AD22
AD5 SCL3/GPIO70 GPIO1 AE22
AE6 SDA3/GPIO69 SCL4/GPIO68 GPIO0 FPGA_LVDS_INFO
AD6 SDA4/GPIO67
AC6 SCL5/GPIO66
AC7 SDA5/GPIO65
IRB_SPI_MISO
IRB_SPI_MOSI
LG1152_RM
IRB_SPI_CK
IC100-*1 IRB_SPI_SS
IR_B_RESET
EMMC_RST
EMMC_CLK
EMMC_CMD
EMMC_DATA[0-7]
OPTIC_FPGA_RESET
OPTIC_SERDES_RESET
3D_DEPTH_RESET
/RST_PHY
OLED_TCON_RESET
HW_OPT_9 +3.3V_NORMAL
HW_OPT_7 SW1
JTP-1127WEM
HW_OPT_8
2 1
DSUB_DET
For ISP
4 3
Delete PV
SC_DET
COMP1_DET DEBUG
HW_OPT_5
HW_OPT_6
M_RFModule_ISP
HW_OPT_10
M_RFModule_RESET
FRC_RESET
HW_OPT_2
HW_OPT_1
HW_OPT_0
+5V_NORMAL
HW_OPT_4
FLASH_WP
/RST_HUB
HW_OPT_3
HP_DET
HDMI_S/W_RESET
RF_SWITCH_CTL
Q104
/TU_RESET
2N7002K
/S2_RESET
Debug
P100
+3.3V_NORMAL
12507WS-04L
OPT
1
DEBUG
2
UART1_RX
D100
3
4
UART1_TX
5
1
LGE Internal Use Only