Pll Frequency Synthesizer - Standard Horizon HX280S Service Manual

Circuit Description
4-1 Automatic Transmit Power Control
Current from the final amplifier is sampled by C1011 &
C1022, and R1004 & R1008, and is rectified by D1002
(RB715F). The resulting DC is fed back through Q1004
( L M 2 9 0 4 P W R ) t o t h e d r i v e a m p l i f i e r Q 1 0 1 3
(R Q A 0 0 0 4 P X D Q S ) and final amplifier Q 1 0 0 9
(RQA0011DNS), for control of the power output.
When the microprocessor selects "High" or "Low" pow-
er levels, pin 66 of Q1025 (UPD78F0484GK) to go low at
" H i g h " p o w e r s e l e c t e d o r p i n 6 6 o f Q 1 0 2 5
(UPD78F0484GK) to go high at "Low" power selected.

5. PLL Frequency Synthesizer

The PLL circuitry on the Main Unit consists of VCO Q1008
(2SC5006), VCO buffer Q1007 (2SC5006), PLL sub-
system IC Q1021 (LV2105V), which contains a reference
divider, serial-to-parallel data latch, programmable divid-
er, phase comparator and charge pump, and crystal X1001
which frequency stability is ±5 ppm @ –20 °C to +60 °C.
While receiving, VCO Q1008 (2SC5006) oscillates be-
tween 134.35 and 141.575 MHz according to the trans-
ceiver version and the programmed receiving frequency.
The VCO output is buffered by Q1007 (2SC5006), then
applied to the prescaler section of Q1021 (LV2105V). There
the VCO signal is divided by 64 or 65, according to a con-
trol signal from the data latch section of Q1021 (LV2105V),
before being sent to the programmable divider section of
Q1021 (LV2105V).
The data latch section of Q1021 (LV2105V) also receives
serial dividing data from the microprocessor Q1025, which
causes the pre-divided VCO signal to be further divided
in the programmable divider section, depending upon the
desired receive frequency, so as to produce a 25.0 kHz
derivative of the current VCO frequency.
Meanwhile, the reference divider sections of Q1021
(LV2105V) divides the 21.25 MHz crystal reference from
the reference oscillator section ofQ1021 (LV2105V), by 850
to produce the 25.0 kHz loops reference.
8
The 25.0 kHz signal from the programmable divider (de-
rived from the VCO) and that derived from the reference
oscillator are applied to the phase detector section of
Q1021 (LV2105V), which produces a pulsed output with
pulse duration depending on the phase difference between
the input signals.
This pulse train is filtered to DC and returned to the Var-
actor D1011 and D1012 (both HVC350B).
Changes in the level of the DC voltage applied to the Var-
actor, affecting the reference in the tank circuit of the VCO
according to the phase difference between the signals
derived from the VCO and the crystal reference oscilla-
tor.
The VCO is thus phase-locked to the crystal reference os-
cillator. The output of the VCO Q1008 (2SC5006) after
buffering by Q1007 (2SC5006) is applied to the first mix-
er as described previously.
For transmission, the VCO Q1008 (2SC5006) oscillates
between 156.025 and 157.425 MHz according to the mod-
el version and programmed transmit frequency. The re-
mainder of the PLL circuitry is shared with the receiver.
However, the dividing data from the microprocessor is
such that the VCO frequency is at the actual transmit fre-
quency (rather than offset for IFs, as in the receiving case).
Also, the VCO is modulated by the speech audio applied
to D1014 (HVC306B), as described previously.
6. Miscellaneous Circuits
Push-To-Talk Transmit Activation
When the PTT switch on the Main Unit is closed, pin 72 of
Q1025 (UPD78F0484GK) goes low. This signal disables
the receiver by disabling the 5 V supply bus at Q1011
(UMD5N) to the front-end, FM IF subsystem IC Q1026
(BA4116FV).
At the same time, Q1010 (UMD5N) activate the transmit 5
V supply line to enable the transmitter.