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Circuit Description
4-1 Automatic Transmit Power Control
Current from the final amplifier Q1009 (RD09MUS2) is
sampled by C1009 and C1020, and rectified by D1003
(RB751F). The resulting DC is compared with the pow-
er control voltage from the RF power controller section
o f t h e D / A I C Q 1 0 3 0 ( B U 2 5 0 2 F S ) b y Q 1 0 0 4
(LM2904PW). As a result, the compared output voltage
controls the bias level of the exciter amplifier Q1015
(RD01MUS1) and final amplifier Q1009 (RD09MUS2),
for control of the power output.
4-2 Spurious Suppression
Generation of spurious products by the transmitter is
minimized by the fundamental carrier frequency being
equal to final transmitting frequency, modulated directly
in the VCO Q1010 (2SC5231). Additional harmonic sup-
pression is provided by a low-pass filter consisting of
coils L1001, L1002, & L1003 and capacitors C1001,
C1004, C1011, C1013, & C1018, resulting in more than
60 dB of harmonic suppression prior to delivery to the
antenna.
5. PLL Frequency Synthesizer
The PLL circuitry on the Main Unit consists of VCO
Q1010 (2SC5231), VCO buffer Q1008 (2SC5006), PLL
subsystem IC Q1026 (LV2105V), which contains a refer-
ence divider, serial-to-parallel data latch, programma-
ble divider, phase comparator, & charge pump, and crys-
tal X1001 (11.7 MHz) which frequency stability is ±10
ppm at –20 °C to +60 °C.
While receiving, VCO Q1010 (2SC5231) oscillates be-
tween 203.300 and 210.525 MHz according to the receiv-
ing frequency. The VCO output is buffered by Q1008
(2SC5006), then applied to the prescaler section of
Q1026 (LV2105V). There the VCO signal is divided ac-
cording to a control signal from the data latch section of
Q1026 (LV2105V), before being sent to the programma-
ble divider section of Q1026 (LV2105V).
The data latch section of Q1026 (LV2105V) also receives
serial dividing data from the microprocessor Q1032
(µPD78F1167GC), which causes the pre-divided VCO
signal to be further divided in the programmable divid-
er section, depending upon the desired receive frequen-
cy, so as to produce a 12.5 kHz derivative of the current
VCO frequency.
Meanwhile, the reference divider sections of Q1026
(LV2105V) divides the crystal X1001 (11.7 MHz) by 936
to produce the 12.5 kHz loops reference (respectively).
8
The 12.5 kHz signal from the programmable divider (de-
rived from the VCO) and that derived from the refer-
ence oscillator are applied to the phase detector section
of Q1026 (LV2105V), which produces a pulsed output
with pulse duration depending on the phase difference
between the input signals. This pulse train is delivered
to the charge pump Q1021 (2SA1774) and Q1022
(2SC4617-R), then filtered to DC and returned to the
Varactor D1008 and D1009 (both HVC350B).
Changes in the level of the DC voltage applied to the Var-
actor, affecting the reference in the tank circuit of the
VCO according to the phase difference between the sig-
nals derived from the VCO and the crystal reference
oscillator.
The VCO is thus phase-locked to the crystal reference
oscillator. The output of the VCO Q1010 (2SC5231) af-
ter buffering by Q1008 (2SC5006), is applied to the first
mixer as described previously.
For transmission, the VCO Q1010 (2SC5231) oscillates
between 156.025 and 157.425 MHz according to the
transmit frequency. The remainder of the PLL circuitry
is shared with the receiver. However, the dividing data
from the microprocessor is such that the VCO frequen-
cy is at the actual transmit frequency (rather than off-
set for IFs, as in the receiving case). Also, the VCO is
modulated by the speech audio applied to D1011
(HVC306B), as described previously.
6. DSC Encoder/Decoder
6-1 Encoder
The microprocessor Q1032 (µPD78F1167GC) encodes
the DSC (Digital Selective Calling) signals. This signal
is input into the IDC section of Q1003 (LM2902PW).
The processes of DSC transmitting are the same as voice
modulation.
6-2 Decoder
The received DSC signals on channel 70 are filtered by a
low-pass filter Q1037 (2SC4617-R). Then this signal is
input into the FSK decoder IC Q1045 (NJM2211M) to con-
vert the analog signal into the digital code. Micropro-
cessor Q1032 (µPD78F1167GC) watches the digital code
and is computing the DSC.
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