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Circuit Description
If a DCS code is enabled for transmission, the code is gen-
erated by microprocessor Q1066 (HD64F2266) and de-
livered to X1001 (21.25 MHz) for DCS modulating.
The modulated signal from the VCO Q1012 (2SC5231) is
buffered by Q1013 (2SC5374). The low-level transmit sig-
nal is then passes through the TX switching diode D1012
(DAN235E) to the buffer amplifier Q1032 (2SC5226),
driver amplifier Q1036 (2SK3074), then amplified trans-
mit signal is applied to the final amplifier Q1045
(RD07MVS1) up to 5.0 watts output power.
The transmit signal then passes through the antenna switch
D1034 (RLS135) and is low-pass filtered to suppress har-
monic spurious radiation before delivery to the antenna.
4-1 Automatic Transmit Power Control
Current from the final amplifier is sampled by C1237,
C1236, C1208, R1273, and R1272, and is rectified by D1035
(1SS321). The resulting DC is fed back through Q1062
(LM2904PW) to the drive amplifier Q1036 (2SK3074) and
final amplifier Q1045 (RD07MVS1), for control of the
power output.
The microprocessor Q1066 (HD64F2266) selects "High"
or "Low" power levels.
4-2 Spurious Suppression
Generation of spurious products by the transmitter is min-
imized by the fundamental carrier frequency being equal
to final transmitting frequency, modulated directly in the
VCO Q1012 (2SC5231). Additional harmonic suppression
is provided by a low-pass filter consisting of coils L1012
and L1013 plus capacitors C1165, C1291, C1167, C1169,
and C1190, resulting in more than 60 dB of harmonic sup-
pression prior to delivery to the antenna.
5. PLL Frequency Synthesizer
The PLL circuitry on the Main Unit consists of VCO Q1012
(2SC5231), VCO buffer Q1013 (2SC5374), PLL subsystem
IC Q1017 (MB15A01PFV1), which contains a reference
divider, serial-to-parallel data latch, programmable divid-
er, phase comparator and charge pump, and crystal X1001
(21.25 MHz) which frequency stability is ±2.5 ppm –30 to
+60 °C.
While receiving, VCO Q1012 (2SC5231) oscillates be-
tween 115.3 and 152.3 MHz according to the transceiver
version and the programmed receiving frequency. The
VCO output is buffered by Q1016 (2SC5374), then ap-
plied to the prescaler section of Q1017 (MB15A01PFV1).
There the VCO signal is divided by 64 or 65, according to
a control signal from the data latch section of Q1017
(MB15A01PFV1), before being sent to the programmable
divider section of Q1017 (MB15A01PFV1).
8
The data latch section of Q1017 (MB15A01PFV1) also re-
ceives serial dividing data from the microprocessor Q1066
(HD64F2266), which causes the pre-divided VCO signal
to be further divided in the programmable divider sec-
tion, depending upon the desired receive frequency, so as
to produce a 5.0 kHz or 6.25 kHz derivative of the current
VCO frequency.
Meanwhile, the reference divider sections of Q1017
(MB15A01PFV1) divides the crystal X1001 (21.25 MHz)
by 3360 (or 2688) to produce the 5.0 kHz (or 6.25 kHz)
loops reference (respectively).
The 5.0 kHz (or 6.25 kHz) signal from the programmable
divider (derived from the VCO) and that derived from
the reference oscillator are applied to the phase detector
section of Q1017 (MB15A01PFV1), which produces a
pulsed output with pulse duration depending on the phase
difference between the input signals. This pulse train is
filtered to DC and returned to the Varactor D1006
(HVC350B).
Changes in the level of the DC voltage applied to the Var-
actor, affecting the reference in the tank circuit of the VCO
according to the phase difference between the signals de-
rived from the VCO and the crystal reference oscillator.
The VCO is thus phase-locked to the crystal reference os-
cillator. The output of the VCO Q1012 (2SC5231) after
buffering by Q1013 (2SC5374), is applied to the first mix-
er as described previously.
For transmission, the VCO Q1012 (2SC5231) oscillates
between 134.00 and 174.00 MHz according to the model
version and programmed transmit frequency. The remain-
der of the PLL circuitry is shared with the receiver. How-
ever, the dividing data from the microprocessor is such
that the VCO frequency is at the actual transmit frequen-
cy (rather than offset for IFs, as in the receiving case). Also,
the VCO is modulated by the speech audio applied to
D1005 (HSC277), as described previously.
6. Miscellaneous Circuits
The PTT switch for the internal microphone is connected
to pin 47 of microprocessor Q1066 (HD64F2266), so that
when the PTT switch is closed, pin 47 of Q1066
(HD64F2266) goes low. This signal disables the receiver
by disabling the 5 V supply bus at Q1029 (DTA143XE) to
the front-end, FM IF subsystem IC Q1039 (NJM2591V).
At the same time, Q1028 (UMW1) and Q1025 (2SA1774)
activate the transmit 5 V supply line to enable the trans-
mitter.
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