Overall Block Diagram (1/8) - Sony HDR-UX3E Service Manual

Digital hd video camera recorder
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3-2. OVERALL BLOCK DIAGRAM (2/8)
UX3E/UX5/UX5E
DRVOUT1, DCOUT1,
DRVOUT4, DCOUT4
DRVOUT2, DCOUT2,
DRVOUT5, DCOUT5
1
DRVOUT3, DCOUT3,
OVERALL (1/8)
DRVOUT6, DCOUT6
(PAGE 3-1)
CHCK2_4M
UX7/UX7E
DRVOUT1, DCOUT1,
DRVOUT5, DCOUT5
DRVOUT2, DCOUT2,
DRVOUT6, DCOUT6
4
DRVOUT3, DCOUT3,
DRVOUT7, DCOUT7
14
OVERALL (1/8)
DRVOUT4, DCOUT4,
(PAGE 3-1)
DRVOUT8, DCOUT8
25
CHCK3_6M
UX3E/UX5/UX5E
XSYS_RST
30
2
TGVD, TGHD
OVERALL (1/8)
(PAGE 3-1)
AHS_SO, AHS_SCK, XCS_AHS
5
PITCH_AD
34
OVERALL (1/8)
YAW_AD
33
(PAGE 3-1)
VST_C_RESET
32
UX7/UX7E
FP-530 FLEXIBLE
BOARD
PNDCK
26
EXT_CAM_VD
14
CAM_SO, CAM_SI, CAM_SCK
XCS_IC_5404
11
UX3E/UX5/UX5E
XIC_5404_RST
10
3
EN1, DIRA1, DIRB1
OVERALL (1/8)
NF_EN, NF_SW
(PAGE 3-1)
LENS_TEMP_AD
22
6
THERM
OVERALL (1/8)
23
(PAGE 3-1)
PITCH_AD
2
YAW_AD
3
VST_C_RST
7
XSYS_RST
8
XRST_IC_5703_CPU
9
IC_2701_SYSCLK
5
UX7/UX7E
05
HDR-UX3E/UX5/UX5E/UX7/UX7E_L2
( ) : Number in parenthesis ( ) indicates the division number of schematic diagram where the component is located.
VC-487 BOARD (1/6)
UX3E/UX5/UX5E
UX7/UX7E
CN1201
DRVOUT1, DCOUT1,
DRVOUT4, DCOUT4,
DRVOUT4, DCOUT4
DRVOUT8, DCOUT8
DRVOUT2, DCOUT2,
Not used
DRVOUT5, DCOUT5
(Connect to GND)
DRVOUT3, DCOUT3,
DRVOUT3, DCOUT3,
DRVOUT6, DCOUT6
DRVOUT7, DCOUT7
DRVOUT2, DCOUT2,
DRVOUT6, DCOUT6
DRVOUT1, DCOUT1,
DRVOUT5, DCOUT5
CHCK2_4M
CHCK3_6M
XSYS_RST
TGVD, TGHD
AHS_SO, AHS_SCK, XCS_AHS
PITCH_AD
YAW_AD
VST_C_RESET
CN1007
PNDCK
EXT_CAM_VD
CAM_SO, CAM_SI, CAM_SCK
XCS_IC_5404
XIC_5404_RST
EN1, DIRA1, DIRB1
NF_EN, NF_SW
LENS_TEMP_AD
THERM
UX3E/UX5/UX5E
PITCH_AD
YAW_AD
VST_C_RST
XSYS_RST
XRST_IC_5703_CPU
IC_2701_SYSCLK
L_EN0
L_DIRA0
L_DIRB0
LENS_COVER_LED_ON
8
LENS_COVER_OPEN
7
OVERALL (7/8)
LENS_COVER_CLOSE
IC_2701_SYSCLK
(PAGE 3-7)
OVERALL (3/8)
DIAL_A
(PAGE 3-3)
DIAL_B
UX7/UX7E
AD0_0 – AD0_13
IC1201
CDS,
AD1_0 – AD1_13
A/D CONVERTER
(1/15)
AD2_0 – AD2_13
K5 D6 D7
F7, E6, E7
F6, G6 H5
AD3_0 – AD3_13
ADC_TGVD, ADC_TGHD
ADC_SO, ADC_SCK, XCS_ADC0
CLPOB
K5 D6 D7
F7, E6, E7
F6, G6 H5
AD1_0 – AD1_13
IC1301
CDS,
A/D CONVERTER
(2/15)
AD3_0 – AD3_13
IC1701
CLOCK
5
GENERATOR
UX7/UX7E
(3/15)
D7
A7
TG_FLD
D13
XCS_IC_1702_BUS
C22
J1
IC_1702_BUS_CLK
B14
K1
D24A00_CAM - D31A07_CAM, DXXA08_CAM - DXXA13_CAM
R22
XSYS_RST
F2
F4
P22
IC1803
HI_SO, HI_SI, XHI_SCK
P23
CAMERA CONTROL
T2
XCS_IC_1803
(4/15)
AC6
SYS_V
B8
F23
A14
EEP_SI, EEP_SO, EEP_SCK
A13
XCS_EEP
D12
F1
AB16
B5
C1
D5
X1802
20MHz
D1
B11
A11
3-2
R1
IC1702
UX3E/UX5/UX5E
CAMERA
SIGNAL
K21
PROCESSOR
(3/15)
X1701
62.370000MHz: UX3E/UX5E
STL_DATA/CCD_IN0 – STL_DATA/CCD_IN13,
80.919081MHz: UX5
0-31
89.010989MHz: UX7
74.250000MHz: UX7E
1
STL_ADDR0 – STL_ADDR11, STL_BS0, STL_BS1
CHCK
U1
AHS_TGVD, AHS_TGHD
A3
A10
AHS_SO, AHS_SCK, AHS_XCS0
CAM_VD_HS
AA6
XSYS_RST
T4
AB4
PNDCK
AC11
EN1, DIRA1, DIRB1
UX7/UX7E
EXT_CAM_VD
AC7
L21
AA3
AC5
STROBE_ON
F23
EXT_STROBE_ON
H22
XSYS_RST
IC1804
128K EEPROM
(4/15)
1
A
: VIDEO SIGNAL
VIN_Y0 – VIN_Y7
VIN_C0 – VIN_C7
VIN_HD, VIN_VD, VIN_FLD
EXT_CAM_CLK
A20
EXT_CAM_VD
B20
IC2101
(1/5)
CPU
(5/15)
IC1902
(6/15)
128M SDRAM
(8/15)
F2
G9
0-15
STL_DATA14, STL_DATA15
STL_CLK
A8
STL_XCS0
C7
J1 J8
IC1901
256M SDRAM
(8/15)
OVERALL (7/8)
9
(PAGE 3-7)
OVERALL (7/8)
10
(PAGE 3-7)
HI_SO, HI_SI, XHI_SCK
XCS_IC_1803
G17
SYS_V
D25

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