Denon DCD-3560 Service Manual page 31

Terminal Terminal
I/O
Terminal Function
No. Symbol
46 RA09 0 Address output of external RAM. ADDR09.
47 RA10
0 Address output of external RAM. ADDR10.
48 RA11
I
0 Address output of external RAM. ADDR11.
49
RAWE
0 Write enable signal output for external RAM. (Active at "L".)
50 RACS 0 Chip select signal output for external RAM. (Active at "L".)
51 C4M
0
Dividing output of X'tal. f ; 4.2336 MHz.
52 V ss
-
GND (OV).
53 XTAI I X'tal oscillation circuit input. By selecting of mode, f ; 8.4672 MHz or 16.9344 MHz.
54 XTAO
0
X'tal oscillation circuit output. By selecting of mode, f ; 8.4672 MHz or 16.9344 MHz.
55 MD1 I Mode selection input 1.
56 MD2
I Mode selection input 2.
57 MD3 I
Mode selection input 3.
58 SLOB
I
Code switching input for audio data output. At "I,.." for 2's compliment output; at "H" for offset binary
output.
59
PSSL
I
I
Mode switching input for audio data output. At "L" for serial output; at "H" for parallel output.
60
APTR
0
Control output for aperture compensation. In "H" for R-ch.
61
APTL
0
Control output for aperture compensation. In "H" for L-eh.
62 DA01
0
At PSSL; "H" for DA01 (LSB of parallel voice data) output.
At PSSL ; "L" for C1 F1 output.
63 DA02 0
At PSSL; "H" for DA02 output;PSSL; "L" for C1 F2 output.
64 DA03
0 At PSSL; "H" for DA03 output; PSSL; "L" for C2F1 output.
65 DA04 0
At PSSL ; "H" for DA04 output; PSSL; "L" for C2F2 output.
66 DA05 .0
At PSSL; "H" for DA05 output; PSSL; "L" for C2FL output.
67 DA06
0 At PSSL; "H" for DA06 output; PSSL ; "L" for C2PO output.
68 DA07
0 At PSSL; "H" for DA07 output; PSSL; "L" for RFCK output.
69 DA08
0 At PSSL ; "H" for DA08 output; PSSL ; "L" for WFCK output.
70 DA09
0 At PSSL; "H" for DA09 output; PSSL; "L" for PLCK output.
71
DA10 0 At PSSL; "H" for DA1 0 output; PSSL; "L" for UGFS output.
72 DA11
0 At PSSL; "H" for DA11 output; PSSL; "L" for GTOP output.
73
VDD
- Power supply (+5V).
74 DA12
0 At PSSL; "H" for DA12 output; PSSL; "L" for RAOV output.
75 DA13 0 At PSSL; "H" for DA13 output; PSSL; "L" for C4LR output.
76 DA14
0 At PSSL; "H" for DA 14 output; PSSL; "L" for C21 0 output.
77
DA1b 0
At PSSL; "H" for DA15 output; PSSL; "L" for C21 0 output.
78 DA16
0
At PSSL; "H" for DA16 (MSB of parallel voice data) output.
At PSSL; "L" for DATA output.
79 WDCK
0 Strobe signal output. At OF ON, 176.4 kHz. At CXD1125Q or OF OFF, 88.2 kHz.
80 LRCK
0 Strobe signal output. At OF ON, 88.2 kHz. At CXDl125Q or OF OFF, 44.1 kHz.
Note:
C1 F1:
J
C1 F2:
C2F1:]
C2F2:
C2FL:
C2PO:
RFCK:
WFCK:
PLCK:
Monitor output for error correction state what C1 is at
decode.
Monitor output for error correction state what C2 is at
decode.
Correction state output. Becomes "H" when C2 system
in which presently under correction is unable to correct.
C2 pointer indication output. Synchronizes with audio
data output.
Read frame clock output. 7.35 kHz of X'tal system.
Write frame clock output. 7.35 kHz when locked on to
X'tal system.
VCO/2 output. When locked to EFM signal, f ; 4.3218
MHz.
UGFS:
GTOP:
RAOV:
C4LR:
C210:
C210:
DATA:
Output of unprotected frame sync pattern.
Indication output of frame synchro in protected condi-
tion.
Overflow and underflow indication outputs of ±4 frame
jitter absorbing RAM.
Strobe signal. At OF ON, 352.8 kHz. At CXD1125Qor
DF OFF, 176.4 kHz.
R~verse
output of C210.
Bit clock output. At OF ON, 4.2336 MHz. At
CXD1125Q or OF OFF, 2.1168 MHz.
Serial data output of audio signal.
31