Sony CDX-C8000R Service Manual page 29

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• IC805 CXD2726Q-4 (DIGITAL SIGNAL PROCESSOR, DIGITAL FILTER, D/A CONVERTER) (DSO BOARD)
Pin No. Pin Name I/O
1 DGND — Ground terminal (digital system)
2 – 15 T.P I Input terminal for the test (fixed at "L")
16 – 21 TST0 – TST5 I Input terminal for the test (fixed at "L")
22 – 24 JPE1 – JPE3 I External condition jump terminal "H": condition jump (fixed at "L")
25 DVDD — Power supply terminal (+3.3 V) (digital system)
26 DA1GND — Ground terminal (for D/A converter 1) (analog system)
D/A converter 1 (L-ch side) output terminal
27 DA1LO O
Analog signal output for front side (L-ch side) output in this set
28 DA1VDD — Power supply terminal (+3.3 V) (for D/A converter 1) (analog system)
D/A converter 1 (R-ch side) output terminal
29 DA1RO O
Analog signal output for rear side (L-ch side) output in this set
30 DA1VDD — Power supply terminal (+3.3 V) (for D/A converter 1) (analog system)
31 DA1GND — Ground terminal (for D/A converter 1) (analog system)
32 ADLVDD — Power supply terminal (+3.3 V) (for L-ch side A/D converter) (analog system)
33 ADLGND — Ground terminal (for L-ch side A/D converter) (analog system)
34 ADLREF O Connected to the bus control for A/D converter (for L-ch side)
A/D converter (L-ch side) analog input terminal
35 ADLIN I
Tuner and bus audio input signal (L-ch side) in this set
36 DA2GND — Ground terminal (for D/A converter 2) (analog system)
37 DA2VDD — Power supply terminal (+3.3 V) (for D/A converter 2) (analog system)
38 DA2LO O D/A converter 2 (L-ch side) output terminal (Not used.)
39 MCKVDD — Power supply terminal (+3.3 V) (for master clock) (analog system)
40 MCKO O System clock output terminal (16.9344 MHz)
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41 MCKI I System clock input terminal (16.9344 MHz)
42 MCKGND — Ground terminal (for master clock) (analog system)
D/A converter 2 (R-ch side) output terminal
43 DA2RO O
Analog signal output for sub woofer output in this set
44 DA2VDD — Power supply terminal (+3.3 V) (for D/A converter 2) (analog system)
45 DA2GND — Ground terminal (for D/A converter 2) (analog system)
A/D converter (R-ch side) analog input terminal
46 ADRIN I
Tuner and bus audio input signal (R-ch side) in this set
47 ADRREF O Connected to the bus control for A/D converter (for R-ch side)
48 ADRGND — Ground terminal (for R-ch side A/D converter) (analog system)
49 ADRVDD — Power supply terminal (+3.3 V) (for R-ch side A/D converter) (analog system)
50 DA3GND — Ground terminal (for D/A converter 3) (analog system)
51 DA3VDD — Power supply terminal (+3.3 V) (for D/A converter 3) (analog system)
D/A converter 3 (L-ch side) output terminal
52 DA3LO O
Analog signal output for rear side (R-ch side) output in this set
53 DA3GND — Power supply terminal (+3.3 V) (for D/A converter 3) (analog system)
D/A converter 3 (R-ch side) output terminal
54 DA3RO O
Analog signal output for front side (R-ch side) output in this set
55 DA3GND — Ground terminal (for D/A converter 3) (analog system)
56 DGND — Ground terminal (digital system)
57 SYSRST I System reset signal input from the master controller (IC502) "L": reset
58 BFOT O Master clock signal output terminal
Serial data transfer clock signal input from the master controller (IC502) and liquid
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59 SCK I
crystal display drive controller (IC701)
Transfer enable signal output to the master controller (IC502)
60 REDY O
"L": transfer prohibition
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Serial data output to the master controller (IC502) and liquid crystal display drive
61 TRDT O
controller (IC701)
62 XLAT I Serial data latch pulse input from the master controller (IC502)
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Pin Description
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Pin No. Pin Name
63 RVDT
64 24/23BIT
65 DVDD
66 DVSS
67 – 69 SO1 – SO3
70 SOUT
71 SI1
72, 73 SI2, SI3
74 SIN
75 BCK
76 LRCK
77 MST/SLV
78 DVDD
79 PLLGND
80 PLLENA
81 22 MHz
82 PLLCNT
83 PLLVDD
84 DGND
85 – 94 T.P
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95 DVDD
96 DRAMGND
97 – 99 T.P
100 DRAMVDD
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2 4 2
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I/O Pin Description
I Serial data input from the master controller (IC502)
Serial data 24/32 bit slot selection signal input terminal
I
"L": 24 bit slot, "H": 32 bit slot (validity at slave mode) (fixed at "L" in this set)
— Power supply terminal (+3.3 V) (digital system)
— Ground terminal (digital system)
O Serial data output terminal (Not used.)
O Serial data output terminal (Not used.)
I Serial data input terminal
I Serial data input terminal Not used (fixed at "L")
I Serial data input terminal Not used (fixed at "L")
I Bit clock signal (2.8224 MHz) input terminal
I L/R sampling clock signal (44.1 kHz) input terminal
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection
I
signal input from the master controller (IC502) "L": master mode, "H": slave mode
— Power supply terminal (+3.3 V) (digital system)
— Ground terminal (PLL system)
I PLL enable signal input terminal Normally: fixed at "L"
O PLL clock signal output terminal (22.5792 MHz) (Not used.)
PLL clock output control signal input from the master controller (IC502)
I At "L" is input: fixed at "L" is PLCLK (pin ia)
At "H" is input: PLL clock signal output from the PLCLK (pin ia)
— Power supply terminal (+3.3 V) (PLL system)
— Ground terminal (digital system)
I Input terminal for the test Normally: fixed at "L"
5 0 8 9 2 4 9 8 2
— Power supply terminal (+3.3 V) (digital system)
— Ground terminal (for D-RAM)
I Input terminal for the test Normally: fixed at "L"
— Power supply terminal (+3.3 V) (for D-RAM)
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