Port Allocation - Icom ID-1 Service Manual

4-5 PORT ALLOCATIONS
4-5-1 CPU (LOGIC-1 UNIT; IC50)
Pin Port
number name
Input port for up/down signal from the
29 MU/D
connected microphone.
Input port for the noise signal from the
32 NOIS
noise detector (MAIN unit; D195).
Input port for the S-meter signal from
31 RSSI the demodulator IC (MAIN unit; IC191,
pin 12).
Input port for CTCSS signal from the
33 TONI low-pass fi lter (MAIN unit, IC1461, pin
1).
Output data signals to the USB con-
42 TXD1
troller (IC550, pin 24).
Input port for data signals from the
43 RXD1 USB controller (IC550, pin 25) via the
(IC553).
I/O port for data signals from/to the
53 SDA
EEPROM (IC54, pin 5).
Outputs clock signal to the EEPROM
54 SCL
(IC54, pin 6).
61 BEEP Outputs beep audio signals.
Input port for reset signal form the re-
71 RESET
set IC (IC52, pin 1).
Outputs control signal to the mode
72 P2RSC switch (MAIN unit; IC551, pin 5) via
the level converter (IC55).
Outputs strobe signal to the 2nd PLL
73 P2STC IC (MAIN unit; IC550, pin 3) via the
level converter (IC55).
Outputs the data signal to the 1st and
2nd PLL ICs (MAIN unit; IC400, pin 15,
74 PDATC
IC550, pin 5) via the level converter
(IC55).
Outputs clock signal to the 1st and 2nd
PLL ICs (MAIN unit; IC400, pin 14,
75 PSCKC
IC550, pin 4) via the level converter
(IC55).
Outputs strobe signal to the 1st PLL
76 P1STC IC (MAIN unit; IC400, pin 16) via the
level converter (IC55).
Outputs control signal to the 5A
(Q1345) and D+5 (Q1347) regulators
77 +5AC via the level converter (IC55).
Low: While the +5 and D+5 regu-
Outputs control signal to the DV/FM
filter switches (MAIN unit; D192,
78 W/NSC
D193) via the level converter (IC55).
High: While DV mode is selected.
Outputs control signal to the mode
switches (MAIN unit; IC1411, IC1670,
79 ADSWC
IC1673) via the level converter (IC55).
Low: While DV mode is selected.
Outputs TX LED control signal.
80 TXLED
High: During transmit.
Outputs RX LED control signal.
82 RXLED High: While receiving or squelch is
Description
lators are activated.
opened.
Pin Port
number name
85 PCON
86 ULCK
87 MMUT
93 SCAN
94 TXS
95 RXS
96 AMUT
102 RMUT
103 AFCSW
105 DACK2
106 DADAT2
107 DACK1
108 DADAT1
128 FSTB
129 MSTRC
130 MDATC
131 MCLKC
132 MRESC
4 - 7
Description
Outputs control signal to the TX power
controller (MAIN unit; Q1250).
Input port for the PLL unlock signal.
High: The PLL circuit is unlocked.
Outputs the microphone mute sig-
nal to the mute switch (MAIN unit;
Q1670).
Low: While microphone audio is
muted.
Outputs scan control signal to the
scan switch (Q400).
High: While scanning.
Outputs the T+5, T+3 regulator
circuits (MAIN unit; Q1336, Q1342)
control signal.
High: During transmit.
Outputs the R+5, R+3 regulator
circuits (MAIN unit; Q1337, Q1343)
control signal.
High: During receive.
Outputs the AF mute signal to the AF
mute switch (MAIN unit; Q1550).
Low: W h i l e d i g i t a l c o d e / c a l l
sign/noise/tone squelch are
closed, the audio level is
set to minimum position or
transmitting.
Outputs the SQL mute signal to the
AF switch (MAIN unit; IC1463, pin 2).
High: While noise or tone squelch
is closed.
Outputs AFC switch (IC352, pin 5)
control signal.
Outputs clock signal to the D/A con-
verter (IC57, pin 7).
Outputs the data signal to the D/A
converter (IC57, pin 6).
Outputs clock signal to the D/A con-
verter (IC56, pin 7).
Outputs the data signal to the D/A
converter (IC56, pin 6).
Outputs strobe signal to the FPGA IC
(IC200).
Outputs strobe signal to the liner
C O D E C I C ( I C 1 ) a n d F P G A I C
(IC200).
Outputs the data signal to the liner
C O D E C I C ( I C 1 ) a n d F P G A I C
(IC200).
Outputs clock signal to the liner
C O D E C I C ( I C 1 ) a n d F P G A I C
(IC200).
Outputs reset signal to the liner
C O D E C I C ( I C 1 ) a n d F P G A I C
(IC200).