Terminal Function - Denon DVD-2910 Service Manual

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W986416 (IC103)
W986416DH (MA: IC103)
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L 13942296513

Terminal Function

Pin No. Pin Name
1, 14, 27 V
CC
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
DQ0-DQ15
45, 47, 48, 50,
51, 53
3, 9, 43, 49 V Q
CC
6, 12, 46, 52 V Q
SS
16 WE
17 CAS
18 RAS
19 CS
20, 21 BS0, BS1
23~26, 22
A0-A11
29~35
28, 41, 54 V
SS
36, 40 NC
37 CKE
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38 CLK
39, 15 UDQM, LDQM Input/Output mask
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V 1
CC
2
DQ0
3
V Q
CC
4
DQ1
5
DQ2
6
V Q
SS
7
DQ3
DQ4
8
V Q
9
CC
DQ5 10
DQ6 11
V Q
12
SS
DQ7 13
V 14
CC
LDQM
15
WE 16
CAS
17
18
RAS
19
CS
20
BS0
BS1 21
A10/AP
22
A0
23
24
A1
25
A2
26
A3
27
Vcc
Function
Power (+3.3V)
Data Input/Output
Power (+3.3V) for I/O buffer Separated power from VCC, to improve DQ noise immunity.
Ground for I/O buffer
Write Enable
Column Address Strobe
Row Address Strobe
Chip Select
Bank Select
Address
Ground
No Connection
Clock Enable
Clock Inputs
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2 9
8
54 V
SS
53
DQ15
52
VssQ
51
DQ14
50
DQ13
49
V Q
CC
48
DQ12
DQ11
47
V Q
46
SS
45 DQ10
44 DQ9
V Q
43
CC
42 DQ8
41 V
SS
NC
40
39 UDQM
38 CLK
37 CKE
36
NC
35
A11
34 A9
33
A8
32 A7
31 A6
30 A5
Q Q
29
A4
3 6 7 1 3 1 5
28
Vss
Description
Power for input buffers and logic circuit inside DRAM.
Multiplexed pins for data output and input.
Separated ground from VSS, to improve DQ noise immunity.
Referred to RAS.
Referred to RAS.
Command input. When sampled at the rising edge of the clock RAS, CAS
and WE define the operation to be executed.
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
Select bank to activate during row address latch time, or bank to read/write
during address latch time.
Multiplexed pins for row and column address. Row address: A0-A11.
Column address: A0-A7. A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank selected by BS0, BS1.
Ground for input buffers and logic circuit inside DRAM.
No Connection
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self Refresh mode is entered.
System clock used to sample inputs on the rising edge of clock.
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The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled
high in read cycle. In write cycle, sampling DQM high will block the write
.
operation with zero latency.
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DVD-2910/955
9 4 2 8
0 5 8 2 9 9 4 2 8
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9 9
9 9