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1

7.1.3 SEQUENCE

A
Power On Sequence
Player section
Power on
Canceling reset of SODC
B
(IC603), Pin 45 "H"
Initial setting
Initialization of
loading mechanism
C
A disc can be loaded
before communication
between the main CPU
and the player section
starts.
After a disc is loaded, loading
and startup processes begin.
D
After a disc is loaded, loading
E
and startup processes begin.
Reading data, etc.
F
88
1
2
MAIN CPU
Power on
Canceling reset of CPU
(IC101), Pin 193 "H"
Initial setting for the CPU
Initialization of the SDRAM
Program transfer from
FLASH to SDRAM
Data and clock output
from Pins 164 and 165
of the CPU (IC101).
Program transfer to the
When data transfer to
FPGA (IC301)
the FPGA is finished,
FPGA_DONE (Pin 71)
becomes high.
Program transfer to the
DSP (IC401, IC402)
Device check
Canceling reset of
peripheral devices
Communications with the
Operation section start.
Communications with the
ATAPI system start.
If the result of the check
Checking result of
is NG, error E70** is
peripheral devices
generated.
Long press processing
of the key In the power ON
If a disc is loaded,
the playback process
starts.
Distinction
CD
between
DVD/CD
DVD
CD playback process
Eject
/MP3 playback
CDJ-1000MK3
2
3
CPU for the Operation section
Power on
Canceling reset of the
CPU (IC1002), Pin 12
Initial setting for the CPU
"POWER ON" is indicated
on the FL display.
Long press processing
of the key In the power ON
Once communication
with the main CPU is
established, the
"POWER ON"
indication disappears.
Input of statuses of keys,
output of display data
3
4
4

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