Sony DMP-1000P Service Manual page 52

Pin No. Pin Name
94 MNT2
95 MNT1
96 DVCC
97 PCSX
98 DCSX
99 SVW
100 VRSR
101 DGND
102 SVBK
103 STRS
104 BSH
105 SRDX
106 SWEX
107 SC6X
108 SHWX
109 SRSX
110 SCSX
111 DGND
112 DVCC
113 ICKI
114 ICKO
115 XGND
116 XOUT
117 XIN
118, 119 DGND
120 SADB
121 SADA
122 DGND
123 MRSX
124 MCSX
125 MWEX
126 DVCC
127 to138 SAD11 to SAD0
139 DGND
140 to147 SDT15 to SDT8
148 DGND
149 DVCC
150 to157 SDT7 to SDT0
158 DGND
159 DVCC
160 to167 MDT0 to MTD7
168 DGND
169 DVCC
170 to176 MDT8 to MTD14
I/O
O
Test monitor output terminal (normally: open)
O Test monitor output terminal (normally: open)
—
Power supply terminal (+5V) (logic system)
O
Chip select signal output to the mechanism controller (IC505)
O
Chip select signal output terminal Not used (open)
I Data write end latch pulse input from the system controller (IC503)
I
Refresh stop request input from the system controller (IC503)
—
Ground terminal (logic system)
O
V blanking interrupt signal output to the system controller (IC503)
O Busy signal output to the system controller (IC503)
O
Status (CPU emancipation of memory bus) output to the system controller (IC503)
I
Data read enable signal input from the system controller (IC503)
I
Data write enable signal input from the system controller (IC503)
I
Chip select signal input from the system controller (IC503)
O
CPU D-RAM access wait control signal output to the system controller (IC503)
I
Row address strobe signal input from the system controller (IC503)
I
Column address strobe signal input from the system controller (IC503)
—
Ground terminal (logic system)
—
Power supply terminal (+5V) (logic system)
I
System clock signal (for INT SG) input from the system controller (IC503)
O
System clock signal output terminal Not used (open)
—
Ground terminal (crystal system)
O
System clock signal output terminal Not used (open)
I
System clock signal input terminal Not used (fixed at "L")
— Ground terminal (logic system)
I
Address signal input for the chip select signal generate Connected to address bus (A14)
I
Address signal input for the chip select signal generate Connected to address bus (A13)
—
Ground terminal (logic system)
O Row address strobe signal output to the D-RAM (IC403)
O
Column address strobe signal output to the D-RAM (IC403)
O
Write enable signal output to the D-RAM (IC403)
—
Power supply terminal (+5V) (logic system)
I Address signal input from the system controller (IC503)
—
Ground terminal (logic system)
Two-way data bus with the system controller (IC503), mechanism controller (IC505) and
I/O
D-RAM (IC509) (upper 8 bit)
—
Ground terminal (logic system)
—
Power supply terminal (+5V) (logic system)
Two-way data bus with the system controller (IC503), mechanism controller (IC505), flash
I/O
memory (IC506), D-RAM (IC509) and floppy disk drive controller (IC2101) (lower 8 bit)
—
Ground terminal (logic system)
—
Power supply terminal (+5V) (logic system)
I/O
Two-way data bus with the D-RAM (IC403) (lower 8 bit)
— Ground terminal (logic system)
—
Power supply terminal (+5V) (logic system)
I/O
Two-way data bus with the D-RAM (IC403) (upper 8 bit)
Description
5-55
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DMP-1000P (AEP)