Wait State Generation And Waitimout Logic; Clock Generation Logic; Disk Bus Selector Logic; Read/Write Data Pulse Shaping Logic - Radio Shack TRS-80 Model 4 Technical Reference Manual

4.1.4 Wait State Generation and WAITIMOUT
Logic
As previously mentioned, a wait state to the CPU can
be initiated by an output to the Drive Select Latch
with D6 set. Pin 5 of U18 will go high after this
operation. This signal is inverted by 1/6 of U1 and is
routed to the CPU board where it forces the Z-80 into
a wait state. The Z-80 will remain in the wait state as
long as WAIT* is low. Once initiated, the wait state
will remain until one of four conditions are satisfied.
One half of U10 (a five input NOR gate) is used to
perform this function. INTRQ, DRQ, RESET, and
WAITIMOUT are the inputs to the NOR gate. If any
one of these inputs are active (logic high), the output
of the NOR gate (U10 pin 6) will go low. This output
is tied to the clear input of the wait latch. This signal,
when low, will clear the Q output (U18 pin 5) and set
the Q* output (U18 pin 6). This condition causes
WAIT* to go high and allows the Z-80 to exit the wait
state. U20 is a 12-bit binary counter which serves as
a watchdog timer to insure that a wait condition will
not persist long enough to destroy dynamic RAM
contents. The counter is clocked by a 1MHz signal
and is enabled to count when its reset pin is low (U20
pin 11). A logic high on U20 pin 11 resets the counter
ouputs. U20 pin 15 is the divide by 1024 output and
is used to generate the signal WAITIMOUT. This
watchdog timer logic will limit the duration of a wait to
l024µsec, even if the FDC chip fails to generate a
data request or an interrupt request.
4.1.5

Clock Generation Logic

A 4MHz crystal oscillator and a divide by 2 and divide
by 4 counter generate the clock signals required by
the FDC board. The basic 4MHz oscillator is
implemented with two invertors (1/3 of U25) and a
quartz crystal (Y1). One half of U24 is used to divide
the basic 4MHz clock by 2 to produce a 2MHz output
at U24 pin 6. This output is again divided by 2 using
the remaining half of U24 to produce a 1 MHz output
at U24 pin 8. The 1MHz clock is used to drive the
clock input of the 1793 FDC chip and the clock input
of the watchdog time (U20).
4.1.6

Disk Bus Selector Logic

As mentioned previously, the Model 4 Floppy Disk
Board supports up to four drives (two internal, two
external). This function is implemented by using two
disk drive interface buses, one for the internal drives
and one for the external drives. J4 is the edge
connector used for the internal drives and J1 is the
edge connector for the external drives. U22 (a quad 2
to 1 data selector) is used to select which set of
inputs from the disk drive buses are routed to the
1793 FDC chip. U22 pin 1 is the control pin for the
data selector. If U22 pin 1 is low, the external inputs
are selected, otherwise the internal inputs are
selected. This control signal (labeled EXTSEL*) is
derived from the outputs of the Drive Select Latch. If
Drive 2 or Drive 3 is selected, U17 pin 1will go low
indicating that an external drive is selected. One half
of U10 (a five input NOR gate) is used to detect when
one of the four drives is selected. The output of this
NOR gate (U10 pin 5) is inverted and is used as the
head load timing and ready signal for the 1793 FDC
chip. Therefore if any drive is selected, the head is
assumed to be loaded and the selected drive is
assumed to be ready.
4.1.7

Read/Write Data Pulse Shaping Logic

Two one-shots (1/2 of U15 and 1/2 of U23) are used
to insure that the read and write data pulses are
approximately 450nsec in duration.
4.1.8

Disk Bus Output Drivers

High current open collector drivers (U21, U9, and U1)
are used to buffer the output signals from the Drive
Select Latch and the FDC chip to the floppy disk
drives. Note from the schematic that each output
signal to the drives has two buffers associated with
each signal, one set is used for the internal drive bus
and the other set is used for the external bus. No
select logic is required for these output signals since
the drive select bits define which drive is active.
4.1.9 Write Precompensation and Clock
Recovery Logic
The Write Precompensation
Recovery logic is comprised of U11 (WD1691), U13
(WD2143) and U14 (LS629), along with a few
passive components. The WD1691 is an LSI device
which minimizes the external logic required to
interface the 1793 FDC chip to a disk drive. With the
use of an external VCO, U14, theWDl69l will derive
the RCLK signal for the 1793, while providing an
adjustment signal for the VCO, to keep the RCLK
synchronous with the read data from the drive. Write
precompensation control signals are also provided by
the WD1691 to interface directly to the WD2143
(U13) clock generator. The Read Clock Recovery
section of the WD1691 has five inputs: DDEN, VCO,
RDD*, WG, and VFOE*/WF. It also has three
outputs: PU, PD*, and RCLK. The inputs VFOE*/WF
and WG when both are low, enable the Clock
Recovery logic. When WG is high, a write operation
is in progress and the Clock Recovery circuits are
disabled regardless of the state of any other inputs.
The Write Precompensation section of the WD1691
was designed to be used with the WD2143 clock
generator. Write Precompensation is not used in
single density mode and the signal DDEN* when high
indicates this condition. In double density mode
(DDEN* = 0), the signals EARLY and LATE are used
to select a phase input (01 - 04) on the leading edge
of WDIN. The STB line is latched high when this
occurs, causing the WD2143 to start its pulse
generation.
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and Read Clock