Fig. No.
Description
1-1
TRS-80 Model 4 Interconnection Diagram
3-1
Model 4 Block Diagram
3-2
RAM Memory
3-3
Timing of U3 & CPU
3-4
Timing of U4
3-5
CPU Video Access Timing
3-6
I/O Bus Timing Diagram
4-1
Write Precompensation Timing
LIST OF FIGURES
iii
Page No.
4
16
20
23
24
25
27
65