Yamaha DSP-A5 Service Manual page 29

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3 7 63 1515 0
IC6 : AK4526A-VQ (CODEC. ADC/DAC)
20-bit 6-channel A/D, D/A Converter
1
SDOS
OCKS 2
3
M/S
BICK 4
LRCK 5
SDTI1 6
7
SDTI2
SDTI3 8
SDTO 9
DAUX 10
DFS 11
Pin Pin
I/O
No. Name
1 SDOS
2 OCKS
TE
3 M/S
L 13942296513
4 BICK
5 LRCK
6 SDTI1
7 SDTI2
8 SDTI3
9 SDTO
10 DAUX
11 DFS
12 DEM1
13 DEM0
14 MCKO
15 DVDD
16 DVSS
17 /PD
18 XTS
19 ICKS1
20 ICKS0
21 CAD1
www 22 CAD0
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TOP VIEW
Function
I Fixed L
I Fixed L
I Fixed L
Audio serial data clock,
I
64fs bit clock input from microcomputer
L/R channel clock,
I
1fs word clock input from microcomputer
I
DAC Audio serial data input 1-3,
I
PCM input from AC3D2av
I
Audio serial data output,audio
O
data for AC3D2av
I Fixed L
I Double speed sampling mode selection
data input from DIR5
I De-emphasis frequency select input 1 (Fixed L)
I De-emphasis frequency select input 0 (Fixed L)
O Unconnected
Power supply (digital)
Ground (digital)
I Power-down and reset, initial clear input
from AC3D2av
I Connected to ground (analog)
I Connected to ground (analog)
I Connected to ground (analog)
I Connected to ground (analog)
I Connected to ground (analog)
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y
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8
LIN+
30
LIN–
29
RIN+
32
33 VREFL
RIN–
31
32 RIN+
31
RIN– LOUT1
27 VR
30 LIN+
29 LIN– ROUT1
28 VR
28 ROUT1
27 LOUT2
LOUT1 25 VR
26
ROUT2
ROUT2
25 LOUT2 26 VR
24 ROUT3
LOUT2
23 VR
23 LOUT3
ROUT3
24 VR
Pin Pin
No. Name
23 LOUT3
24 ROUT3
Q Q
25 LOUT2
3 6 7 1 3
26 ROUT2
27 LOUT1
28 ROUT1
29 LIN–
30 LIN+
31 RIN–
32 RIN+
33 VREFL
34 VCOM
35 VREFH
36 AVDD
37 AVSS
38 XTI
39 MCKI
40 P/S
41 /CS
42 CCLK
43 CDTI
44 CDTO
u163
.
2 9 9 4 2 8
Audio
ADC HPF
I/F
ADC HPF MCLK
LPF DAC
LRCK
LPF DAC
BICK
SDOUT
LPF DAC
SDIN1
SDIN2
LPF DAC
SDIN3
LPF DAC
LPF DAC
I/O Function
O Lch analog output 3, for CENTER
O Rch analog output 3, for LFE
O Lch analog output 2, for REAR
1 5 0 5 8 2 9 9 4
O Rch analog output 2, for REAR
O Lch analog output 1, for FRONT
O Rch analog output 1, for FRONT
I Lch negative analog input, from MAIN
I Lch positive analog input, from MAIN
I Rch negative analog input, from MAIN
I Rch positive analog input, from MAIN
I Reference voltage (Low) input (analog)
O Common voltage output
I Reference voltage (High) input (analog)
Power supply (analog)
Ground (analog)
Unconnected
External master clock input, 256fs bit
I
clock input from DIR5
I Fixed L
Chip select in serial mode, chip enable
I
from microcomputer
Control data clock in serial mode,
I
serial clock from microcomputer
Control data input in serial mode,
I
serial data from microcomputer
O Unconnected
m
co
DSP-A5
9 9
Clock Gen.
1/2
LRCK
5
BICK
4
DAUX
10
DEM0
13
DEM1
12
DEM
DFS
11
SDOS
1
SDTO
9
6 SDTI1
7 SDTI2
SDTI3
8
2 8 9 9
28