Yamaha DSP-A5 Service Manual page 28

DSP-A5
QQ
3 7 63 1515 0
IC5 : IS61C1024-20J (1M SRAM)
131072-word x 8-bit High Speed Static RAM
NC 1
2
A3
A4 3
4
A5
A6 5
6
A7
A8 7
TOP VIEW
8
A9
A10 9
10
A11
A12 11
12
A13
D1 13
14
D2
D3 15
16
GND
NOTE)
A0-A16:
D1-D8:
/CE1,CE2: Chip enable input 1,2
/OE:
/WE:
IC7 : AK4324-VF-E2 (DAC)
1-bit D/A Converter TE
L 13942296513
DVSS 1
2
DVDD
CKS 3
4
MCLK
/PD 5
6
BICK
SDATA 7
8
LRCK
SMUTE 9
10
DFS
DEM0 11
12
DEM1
Pin Pin
I/O Function
No. Name
1 DVSS Ground (digital)
2 DVDD Power supply (digital)
3 CKS I Master clock (MCLK) select input (Fixed L)
Normal speed (L:256fs, H:384fs)
High speed (L:128fs, H:192fs)
4 MCLK I 256fs bit clock input from DIR5
5 /PD I Power-down and reset, initial clear input from
www
AC3D2av (L:Reset)
6 BICK I 64fs bit clock input from DIR5
7 SDATA I Serial data input from AC3D2av
.
8 LRCK I 1fs word clock input from DIR5
9 SMUTE I Soft mute detect input (H:Soft mute, L:off)
10 DFS I Double speed sampling mode select input from
DIR5 (L:Normal speed, H:High speed)
27
http://www.xiaoyu163.com
32 VCC
31
A2
30 CE2 A0-A16
29
/WE
28 A1
27
A0
26 A16
D1-D8
25
A15
24 /OE
23
A14 /CE1
22 /CE1
21
D8
20 D7
19
D6
18 D5
17
D4
Address input
Data input/output
Output enable input
Write enable input
24 DZFL
23 DZFR LRCK
BICK
22 AVDD
SDATA
21 VREF
20 AVSS
19 AOUTL+
TOP VIEW
SMUTE
18 AOUTL-
17 AOUTR+
16 AOUTR-
15
DIF2
14 DIF1
13
DIF0
x ao
y
i
http://www.xiaoyu163.com
8
27,28
31,
DECODER
2-12,
23,25
26
I/O DATA
13-15,
17-21
CONTROL
22
CE2
30
CONTROL
CIRCUIT
/WE
29
/OE
24
Mode /WE /CE1 /CE2
Not Selected X H X
(Power-down) X X L
Output Disabled
H L H
Read
H L H
Write L L H
NOTE) H: High Level L: Low level
Q Q
3 6 7 1 3
DIF0 DIF1 DIF2 DEM0
13 14 15 11
8
SERIAL INPUT DE-EMPHASIS
6
INTERFACE CONTROL
7
∆∑
8x
/PD
5
INTERPOLATOR MODULATOR
9
∆∑
8x
INTERPOLATOR MODULATOR
DFS
10
CLOCK
DIVIDER
4 3 2
MCLK CKS DVDD
Pin Pin
I/O
No. Name
11 DEM0 I De-emphasis frequency select input 0 (Fixed H)
12 DEM1 I De-emphasis frequency select input 1 (Fixed L)
13 DIF0 I Digital input format input 0 (Fixed L)
14 DIF1 I Digital input format input 1 (Fixed H)
15 DIF2 I Digital input format input 2 (Fixed L)
16 AOUTR- O Rch negative analog output
17 AOUTR+ O Rch positive analog output
18 AOUTL- O Lch negative analog output
19 AOUTL+ O Lch positive analog output
u163
20 AVSS Ground (analog)
.
21 VREF I Reference voltage input
22 AVDD Power supply (analog)
23 DZFR O Rch zero input detect output
24 DZFL O Lch zero input detect output
2 9 9 4 2 8
131072-word x 8-bit
MEMORY ARRAY
(512-row x 2048-column)
COLUMN I/O
32 VCC
16 GND
/OE Data I/O Power
X High impedance
Standby
X High impedance On
High impedance On
H
Output On
L
Input On
X
X: Don't care
1 5 0 5 8 2 9 9 4
DEM1 AVDD AVSS
12 22 20
24
DZFL
19
AOUTL+
SCF
18
AOUTL-
17 AOUTR+
SCF
16 AOUTR-
23 DZFR
1 21
DVSS VREF
Function
m
co
9 9
2 8 9 9