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PCI to Physical Memory Address
The address space here is a hardware-specific variant of sparse-space encoding. For
the CSRs, addr_h<27:6> specifies a longword address where addr_h<5:0> must be
zero. All the 21174 registers are accessed with a LW granularity. For more specific
details on the 21174 CSRs, see the Digital Semiconductor 21174 Core Logic Chip
Technical Reference Manual. For the flash ROM, addr_h<30:6> defines a byte
address. The fetched byte is always returned in the first byte lane (bits <7:0>).
1.12 PCI to Physical Memory Address
Incoming PCI addresses (32-bit or 64-bit) have to be mapped to the 21164 cached
memory space (8GB). The 21174 provides five programmable address windows that
control access of PCI peripherals to system memory.
The mapping from the PCI address to the physical address can be direct, direct
mapped (physical mapping with an address offset), or scatter-gather mapped
(virtual mapping). These five address windows are referred to as the PCI target
windows.
Window 4 maps directly, using the "Monster Window" with dual-address cycles
(DAC), where ad<33:0> equals addr_h<33:0>.
The following three registers are associated with windows <3:0>:
•
Window base (W_BASE) register
•
Window mask (W_MASK) register
•
Translated base (T_BASE) register
In addition, there is an extra register associated with window 3 only. This is the win-
dow DAC register and is used for PCI 64-bit addressing (that is, the DAC mode).
The following text applies only to windows <3:0>.
The window mask register provides a mask corresponding to ad<31:20> of an
incoming PCI address. The size of each window can be programmed to be from
1MB to 4GB in powers of two, by masking bits of the incoming PCI address using
the window mask register, as shown in Table A–12. (Note that the mask field pattern
was chosen to speed up timing-critical logic circuits.)
System Address Space
A–32
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