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Note:
For more detail, please refer to the Intel 82378 System I/O Manual.
As shown in Figure 1–24, PCI window 0 in the 21174 can be enabled to accept the
mem_cs_l signal as the PCI memory decode signal. With this path enabled, the PCI
window hit logic simply uses the mem_cs_l signal. For example, if mem_cs_l is
asserted, then a PCI window 0 hit occurs and the devsel signal is asserted on the PCI.
Figure 1–24 mem_cs_l Logic
PCI Address
Wn_BASE
Wn_MASK
W0_BASE<MEMCS_ENABLE>
Consequently, the window address area must be large enough to encompass the
mem_cs_l region programmed into the PCI-EISA bridge. The remaining window
attributes are still applicable and/or required:
•
The Wx_BASE_SG bit in the W0_BASE register determines if scatter-gather or
direct-mapping is applicable.
•
The W0_ MASK register size information must match the mem_cs_l size for the
scatter-gather and direct-mapping algorithms to correctly use the translated base
register.
•
The mem_cs_l enable bit, W0_BASE<MEMCS_ENABLE>, takes precedence
over W0_BASE<W_EN>.
Suggested Use of a PCI Window
Window 0
Hit Detect
Logic
mem_cs_l
1
0
devsel
LJ-04280.AI4
System Address Space
A–47
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