Samsung AlphaPC 164UX Technical Reference Manual
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Samsung AlphaPC 164UX Technical Reference Manual

Samsung AlphaPC 164UX Technical Reference Manual

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AlphaPC 164UX/BX Motherboard
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  • Page 1 AlphaPC 164UX/BX Motherboard Technical Reference Manual Preliminary...
  • Page 2 Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

  • Page 3: Table Of Contents

    2–5 AlphaPC 164UX Connector Pinouts ........
  • Page 4 AlphaPC 164UX Bcache Interface ........
  • Page 5 Power and Environmental Requirements Power Requirements ..........5–1 Environmental Requirements .
  • Page 6 Enclosure ............B–4 Support, Products, and Documentation Index...
  • Page 7 AlphaPC 164UX L3 Bcache Array ........
  • Page 8 2–1 AlphaPC 164UX Jumper/Connector List ........
  • Page 9 SCSI Controller which are not on AlphaPC 164BX motherboard. The size of AlphaPC 164BX motherboard’s L3 cache is 2MB. • The size of AlphaPC 164UX motherboard’s L3 cache is 2MB or 4MB. • Except the above, AlphaPC 164UX motherboard and 164BX motherboard are •...
  • Page 10 As outlined on the next page, this manual includes the following chapters, appen- dixes, and an index. Chapter 1, Introduction to the AlphaPC 164UX motherboard, is an overview of • the AlphaPC 164UX motherboard, including its components, features, and uses.
  • Page 11 Conventions This section defines product-specific terminology, abbreviations, and other conven- tions used throughout this manual. Abbreviations Register Access • The following list describes the register bit and field abbreviations: Bit/Field Abbreviation Description RO (read only) Bits and fields specified as RO can be read but not written. RW (read/write) Bits and fields specified as RW can be read and written.
  • Page 12 Caution Cautions indicate potential damage to equipment, software, or data. Data Field Size The term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data field of nn contiguous NATURALLY ALIGNED bytes. For example, INT4 refers to a NATURALLY ALIGNED longword.
  • Page 13 Memory figures have addresses starting at the top and increasing toward the bottom. Schematic References Logic schematics are included in the AlphaPC 164UX design package. In this man- ual, references to schematic pages are printed in italics. For example, the following specifies schematic page 26: “.
  • Page 14 is accessible to the process in its current access mode. UNPREDICT- ABLE results may be unchanged from their previous values. Operations that produce UNPREDICTABLE results might also pro- duce exceptions. – An occurrence specified as UNPREDICTABLE may or may not hap- pen based on an arbitrary choice function.

  • Page 15: Introduction To The Alphapc 164Ux Motherboard

    The board also provides a platform for PCI I/O device hardware and software devel- opment. 1.1 System Components and Features The AlphaPC 164UX is implemented in industry-standard parts and uses a Samsung Alpha 21164 microprocessor running at 400,433,466,500,533,600,633,and 667MHz. Figure 1-1 shows the board’s functional components.

  • Page 16: Alphapc 164Ux Functional Block Diagram

    System Components and Features Figure 1–1 AlphaPC 164UX Functional Block Diagram Index Control Alpha 21164 Microprocessor 2/4MB L3 Bcache Tag Data Pdata 128-Bit Data Data Switches Pecc (X5) 168-Pin Unbuffered Control SDRAM DIMM Sockets Address DECchip 21174-CA (X6) Control, I/O Interface,...

  • Page 17: Digital Semiconductor 21174 Core Logic Chip

    100 MHz or faster speed. Two DIMMs provide 32Mb to 512MB of memory, while six DIMMs provide up to 1536MB. Table 1–1 lists the DIMM sizes tested Table 1–1 AlphaPC 164UX SDRAM Memory Configurations (Sheet 1 of 3) Bank 0...
  • Page 18 System Components and Features Table 1–1 AlphaPC 164UX SDRAM Memory Configurations (Sheet 2 of 3) Bank 0 Bank 1 Bank 2 Total Memory 192MB 64MB 64MB 32MB 32MB 224MB 64MB 64MB 32MB 32MB 16MB 16MB 256MB 64MB 64MB 32MB 32MB...

  • Page 19: L3 Bcache Subsystem Overview

    - To populate a bank,you must use 2 matched DIMMs. 1.1.3 L3 Bcache Subsystem Overview The AlphaPC 164UX board-level L3 backup cache (Bcache) is a 2MB, direct- mapped, synchronous SRAM with a 128-bit data path. The board is capable of han- dling an L3 cache size of 4MB.

  • Page 20: Pci Interface Overview

    System Components and Features 1.1.4 PCI Interface Overview The AlphaPC 164UX PCI interface is the main I/O bus for the majority of functions (SCSI interface, graphics accelerator, and so on). The PCI interface has a 33-MHz data transfer rate. An onboard PCI-to-ISA bridge is provided through an Intel 82371SB (SIO) chip.An onboard PCI-to-PCI bridge is provided through an DEC...

  • Page 21: Software Support

    Windows NT. This firmware initializes the system and enables you to install and boot the Windows NT operating system. The ARCSBIOS firmware resides in the flash ROM on the AlphaPC 164UX motherboard. Binary images of the ARCSBIOS firmware are included in the Firmware update diskette, along with a license describing the terms for use and distribution.

  • Page 22: System Configuration And Connectors

    This chapter describes the AlphaPC 164UX configuration, board connectors and functions, and jumper functions. It also identifies jumper and connector locations. The AlphaPC 164UX uses jumpers to implement configuration parameters such as system speed and boot parameters. These jumpers must be configured for the user’s environment.

  • Page 23: Alphapc 164Ux Jumper/Connector Location

    Figure 2–1 AlphaPC 164UX Jumper/Connector Location Yellow wire wire wire Pwr LED Switch IDE LED Reset Switch SCSI LED System Configuration and Connectors 2–2...

  • Page 24: Alphapc 164Ux Jumper Configuration

    Reset switch connector 2.1 AlphaPC 164UX Jumper Configuration The AlphaPC 164UX has one set of jumpers located at J28. These jumpers set the hardware configuration and boot options. Figure 2–1 shows the jumper location on the AlphaPC 164UX motherboard. Figure 2–2 shows the jumper functions for each group.

  • Page 25: Alphapc 164Ux Configuration Jumpers

    Figure 2–2 AlphaPC 164UX Configuration Jumpers J28 System Configuration Jumpers Option 1 Option1 Option2 Option3 Option4 Frequency Option 2 300 MHz 333 MHz Option 3 366 MHz 400 MHz Option 4 433 MHz 466 MHz Option 5 500 MHz 533 MHz...

  • Page 26: Cpu Speed Selection (Option 1,2,3,&4)

    ROM. With the jumper out the ARCSBIOS firmware is loaded. With the jumper in, the Safe ARCSBIOS is loaded. 2.5 AlphaPC 164UX Connector Pinouts This section lists the pinouts of all AlphaPC 164UX connectors. See Figure 2–1 for connector locations. 2.5.1 PCI Bus Connector Pinouts Table 2–2 shows the PCI bus connector pinouts.
  • Page 27 AlphaPC 164UX Connector Pinouts Table 2–2 PCI Bus Connector Pinouts (Sheet 2 of 3) Signal Signal Signal Signal — — — RST# GNT# — AD<30> AD<28> AD<26> AD<24> IDSEL AD<22> AD<20> AD<18> AD<16> FRAME# TRDY# STOP# STOP# SDONE SBO# AD<15>...
  • Page 28 AlphaPC 164UX Connector Pinouts Table 2–2 PCI Bus Connector Pinouts (Sheet 3 of 3) Signal Signal Signal Signal D<42> D<40> D<38> D<36> D<34> D<32> — — — C/BE#<6> C/BE#<4> D<63> D<61> D<59> D<57> D<55> D<53> D<51> D<49> D<47> D<45> D<43>...

  • Page 29: Isa Expansion Bus Connector Pinouts (J10)

    AlphaPC 164UX Connector Pinouts 2.5.2 ISA Expansion Bus Connector Pinouts Table 2–3 shows the ISA expansion bus connector pinouts. Table 2–3 ISA Expansion Bus Connector Pinouts (J10) Signal Signal Signal Signal IOCHCK# RSTDRV IRQ9 –5V DRQ2 –12V ZEROWS# +12V IOCHRDY...

  • Page 30: Sdram Dimm Connector Pinouts (U3 Through U8)

    AlphaPC 164UX Connector Pinouts 2.5.3 SDRAM DIMM Connector Pinouts Table 2–4 shows the SDRAM DIMM connector pinouts. Table 2–4 SDRAM DIMM Connector Pinouts (U3 through U8) (Sheet 1 of 2) Signal Signal Signal Signal 3.3V DQ10 DQ11 DQ12 DQ13 3.3V...

  • Page 31: Eide Drive Bus Connector Pinouts (J24)

    Pins 1 through 84 are on the front side and pins 85 through 168 are on the back side. The AlphaPC 164UX uses BA1 as both BA1 and ADDR12. Therefore, four-bank DIMMs using ADDR<11:0> are the maximum size. (Two-bank DIMMs can use ADDR<12:0>.) Pull-down.

  • Page 32: Diskette (Floppy) Drive Bus Connector Pinouts (J33)

    AlphaPC 164UX Connector Pinouts 2.5.5 Diskette Drive Bus Connector Pinouts Table 2–6 shows the diskette (floppy) drive bus connector pinouts. Table 2–6 Diskette (Floppy) Drive Bus Connector Pinouts (J33) Signal Signal Signal Signal DEN0 DEN1 INDEX MTR0 MTR1 STEP WDATA...

  • Page 33: Com1/Com2 Serial Line Connector Pinouts (J12)

    AlphaPC 164UX Connector Pinouts 2.5.7 COM1/COM2 Serial Line Connector Pinouts Table 2–8 shows the COM1/COM2 serial line connector pinouts. Table 2–8 COM1/COM2 Serial Line Connector Pinouts (J12) COM1 Pin COM2 Pin (Top) COM1 Signal (Bottom) COM2 Signal DCD1 DCD2 RxD1...

  • Page 34: Input Power Connector Pinouts (J18)

    AlphaPC 164UX Connector Pinouts 2.5.9 Input Power Connector Pinouts Table 2–10 shows the input power connector pinouts. Table 2–10 Input Power Connector Pinouts (J18) Voltage Voltage Voltage Voltage +3.3 V dc +3.3 V dc +5 V dc +5 V dc...

  • Page 35: Fast And Wide Scsi Bus Connector

    AlphaPC 164UX Connector Pinouts 2.5.11 Fast and Wide SCSI Bus Connector Table 2–12 shows the Fast and Wide SCSI bus connector pinouts Table 2–12 Fast and Wide SCSI Connector Pinouts (J15) Signal Signal Signal Signal TERMPWR1 18 TERMPWR1 19 SD12...

  • Page 36: Pin Power Led Connector Pinouts

    AlphaPC 164UX Connector Pinouts 2.5.13 Speaker Connector Pinouts Table 2–14 shows the speaker connector pinouts. Table 2–14 Speaker Connector Pinouts (J23) Signal Name SPKR Speaker output — — — 2.5.14 Microprocessor Fan Power Connector Pinouts Table 2–15 shows the microprocessor fan power connector pinouts.

  • Page 37: Soft Power Connector Pinouts

    AlphaPC 164UX Connector Pinouts 2.5.16 IDE Drive LED Connector Pinouts Table 2–17 shows the IDE drive LED connector pinouts. Table 2–17 IDE Drive LED Connector Pinouts (J29) Signal Name ACTIVITY Hard drive active ACTIVUTYPULLUP 2.5.17 Reset Switch Connector Pinouts Table 2–18 shows the reset switch connector pinouts.

  • Page 38: Functional Description

    Functional Description This chapter describes the functional operation of the AlphaPC 164UX. The descrip- tion introduces the Digital Semiconductor 21174 core logic chip and describes its implementation with the 21164 microprocessor, its supporting memory, and I/O devices. Figure 1–1 shows the AlphaPC 164UX major functional components.

  • Page 39: Alphapc 164Ux Bcache Interface

    The 21164 microprocessor controls the board-level L3 backup cache (Bcache) array (see Figure 3–1). The data bus (pdata<127:0>), check bus (pecc<15:0>), p_tag_dirty and p_tag_ctl_par signals are shared with the system interface. Figure 3–1 AlphaPC 164UX L3 Bcache Array Bcache 21164 index<21:4>...

  • Page 40: Main Memory Interface

    Digital Semiconductor 21174 Core Logic Chip Figure 3–2 shows the AlphaPC 164UX implementation of the 21174 core logic chip. Figure 3–2 Main Memory Interface DIMM 0 DIMM 1 DIMM 2 Data pdata<127:0> mdata<128:0> Switches DIMM 3 mecc<15:0> pecc<15:0> (X5) 21164...

  • Page 41: Main Memory Interface

    Semiconductor 21174 Core Logic Chip Technical Reference Manual. 3.2.3 PCI Devices The AlphaPC 164UX uses the PCI bus as the main I/O bus for the majority of peripheral functions. As Figure 3–3 shows, the board implements the ISA bus as an expansion bus for system support functions and for relatively slow peripheral devices.

  • Page 42: Alphapc 164Ux Pci Bus Devices

    Digital Semiconductor 21174 Core Logic Chip Figure 3–3 AlphaPC 164UX PCI Bus Devices 21174 pc164ux.8-10 Primary PCI Bus 21052 21143 82371SB PCI to PCI Ethernet SIO Bridge Controller Bridge pc164ux.28 pc164ux.26 pc164ux.19 ISA Bus PCI64 Secondary PCI Bus Slot 0...

  • Page 43: System-Io (Sio) Chip

    Digital Semiconductor 21174 Core Logic Chip The bridge from the 21164 system bus to the 64-bit PCI bus is provided by the 21174 chip. It generates the required 32-bit PCI address for 21164 I/O accesses directed to the PCI. It also accepts 64-bit double address cycles and 32-bit single address cycles. How- ever, the 64-bit address support is subject to some constraints.

  • Page 44: Pci-Ultra Scsi (Fast-20) I/O Processor Chip

    Digital Semiconductor 21174 Core Logic Chip • Supports PCI and CardBus interfaces • Supports an unlimited PCI burst • Supports PCI clock speed frequency from dc to 33 MHz; network operation with PCI clock from 20 MHz to 33 MHz •...

  • Page 45: Isa Bus Devices

    ISA Bus Devices 3.2.7 PCI Expansion Slots Six dedicated PCI expansion slots are provided on the AlphaPC 164UX. This allows the system user to add additional 32-bit or 64-bit PCI options. While both the 32-bit and the 64-bit slots use the standard 5-V PCI connector and pinout, +3.3 V is sup- plied for those boards that require it.

  • Page 46: Combination Controller

    ISA Bus Devices 3.3.1 Combination Controller The AlphaPC 164UX uses the Standard Microsystems Corporation FDC37C666 Super I/O combination controller chip (see Figure 3–4). It is packaged in a 100-pin QFP configuration. The chip provides the following ISA peripheral functions: •...

  • Page 47: Xd Bus Device

    3.3.3 ISA Expansion Slots One ISA expansion slot is provided for plug-in ISA peripheral (J10). 3.3.4 ISA I/O Address Map Table 3–1 lists the AlphaPC 164UX ISA I/O space address mapping. Table 3–1 ISA I/O Address Map Range (hex) Usage...

  • Page 48: Interrupts

    SIO. However, the AlphaPC 164UX system has more external interrupts than the SIO can handle. They are sent to an external Shift Registers. This Shift Registers takes these interrupts with parallel.

  • Page 49: Interrupt Logic

    Interrupts Figure 3–5 Interrupt Logic Functional Description 3–12...

  • Page 50: Alphapc 164Ux System Interrupts

    Interrupts Table 3–2 AlphaPC 164UX System Interrupts 21164 Interrupt Suggested Usage AlphaPC 164UX Usage irq<0> Corrected system error Corrected ECC error and sparse space reserved encod- ings detected by the 21174 irq<1> — PCI and ISA interrupts irq<2> Interprocessor and timer interrupts irq<3>...

  • Page 51: Isa Interrupts

    Interrupts Table 3–3 ISA Interrupts Interrupt Number Interrupt Source IRQ0 Internal timer IRQ1 Keyboard IRQ2 Interrupt from controller 2 IRQ3 COM2 IRQ4 COM1 IRQ5 Available IRQ6 Diskette (floppy) IRQ7 Parallel port *IRQ8 Reserved IRQ9 Available IRQ10 Available IRQ11 Available IRQ12 Mouse IRQ13 Available...

  • Page 52: System Clocks

    3.6 System Clocks Figure 3–6 shows the AlphaPC 164UX clock generation and distribution scheme. The AlphaPC 164UX system includes input clocks to the microprocessor as well as clock distribution for the various system memory and I/O devices. There are other miscellaneous clocks for ISA bus support.

  • Page 53: Alphapc 164Ux System Clocks

    System Clocks Figure 3–6 AlphaPC 164UX System Clocks Clock Gen Oscclkin (Fast) 21164 TQ2061 *Oscclkin Microprocessor pc164ux.4 Refclkout Clock Gen Oscillator (Slow) CY2308 CY2907 pc164ux.4 pc164ux.4 pc164ux.2 Sysclk DIMM0 buf_dramclkax2 DIMM1 buf_dramclkbx2 21174 DIMM2 buf_dramclkcx2 DIMM3 buf_dramclkdx2 DIMM4 buf_dramclkex2 DIMM5...

  • Page 54: Reset And Initialization

    Reset and Initialization At system reset, the 21164 microprocessor’s procirq<3:0> pins are driven by the clock divisor values set by four jumpers on J28. During normal operation, these sig- nals are used for interrupt requests. The pins are either switched to ground or pulled up in a specific combination to set the 21164 microprocessor’s internal divider.

  • Page 55: Dc Power Distribution

    DC Power Distribution 3.8 DC Power Distribution The AlphaPC 164UX drives its system power from a user-supplied PC power sup- ply. The power supply must provide +12 V dc and -12 V dc, -5 V dc, +3 V dc, and +5 V dc (Vdd).

  • Page 56: Alphapc 164Ux Power Distribution

    DC Power Distribution Figure 3–8 AlphaPC 164UX Power Distribution Functional Description 3–19...

  • Page 57: Upgrading The Alphapc 164Ux

    All DIMMs must be of equal size if they are in the same bank. 4.1 Upgrading SDRAM Memory You can upgrade memory in the AlphaPC 164UX by adding more DIMMs or replac- ing the ones that you have with a greater size.

  • Page 58: Preparatory Information

    ESD approved workstations, or exercising other good ESD prac- tices is recommended. A Samsung 21164 microprocessor with a higher speed rating is available from your local distributor. See Appendix B for information about supporting products. When replacing the microprocessor chip, also replace the thermal conducting GRAFOIL pad.

  • Page 59: Installing The 21164 Microprocessor

    6. Install the heat sink and heat-sink fan as directed in the following steps. A heat- sink/fan kit is available from the vendor listed in Appendix B. Refer to Figure 4–1 for heat-sink and fan assembly details. Upgrading the AlphaPC 164UX 4–3...

  • Page 60: Fan/Heat-Sink Assembly

    2. Wearing clean gloves, pick up the GRAFOIL pad. Do not perform this with bare hands because skin oils can be transferred to the pad. 3. Place the GRAFOIL pad on the gold-plated slug surface and align it with the threaded studs. Upgrading the AlphaPC 164UX 4–4...
  • Page 61 4. Plug the fan power/sensor cable into connector J35. Important: When installing the microprocessor, you must change the frequency of its clock output by setting the system clock divisor jumpers, as described in Section 2.2. Upgrading the AlphaPC 164UX 4–5...

  • Page 62: Power And Environmental Requirements

    Power and Environmental Requirements 5.1 Power Requirements The AlphaPC 164UX motherboard requires a minimum of a 300 watt power supply. The power supply must be ATX-compliant. Table 5–1 Power Supply DC Current Requirements Voltage Current ± +3.3 Vdc, 14 A ±...

  • Page 63: Physical Parameters

    All holes and board measurements are compliant with the ATX 2.01 specification. The AlphaPC 164UX exceeds the ATX height indications in two places. The first is (the 2.5’ region).The second is at the location of the SCSI connectors(the 1.0’ region to the left of the second PCI slots).

  • Page 64: Board Measurements And Hole Locations

    Physical Parameters 5.3.2 Board Measurements and Hole Locations Figure 5–1 shows the Board Measurements and Hole Locations for the AlphaPC 164UX. Figure 5–1 Board measurement and Hole Position Diagram .400" 9.600" .250" .650" .250" 3.1" Board Measurements and Hole Locations 1.300"...

  • Page 65: Board Vertical Clearance

    Physical Parameters 5.3.3 Board Vertical Clearance Figure 5–2 shows the Board Vertical Clearance for the AlphaPC 164UX. Figure 5–2 Board Vertical Clearance Diagram 0.5" 1.0" 2.5" 1.5" 1.5" 1.0" 0.5" Vertical Clearance Requirements Power and Environmental Requirements 5–4...

  • Page 66: Atx I/O Shield Requirements

    Physical Parameters 5.3.4 ATX I/O Shield Requirements Figure 5–3 shows the ATX I/O shield dimensions for the AlphaPC 164UX. Figure 5–3 ATX I/O Shield Dimensions Standard 9 pin DSUB connector cutouts with these center points 4.924 Standard 25 pin 3.454 DSUB connector 2.436...

  • Page 67: System Address Space

    System Address Space This appendix describes the mapping of 21164 40-bit physical addresses to memory and I/O space addresses. It also describes the translation of a 21164-initiated address (addr_h<39:4>) into a PCI address (ad<63:0>) and the translation of a PCI-initiated address into a physical memory address.

  • Page 68: Physical Address Map (Byte/Word Mode Enabled)

    Address Map Table A–1 Physical Address Map (Byte/Word Mode Disabled) (Sheet 2 of 2) 21164 Address Size (GB) Selection 87.2000.0000 – 87.3FFF.FFFF 0.50 PCI special/interrupt acknowledge 87.4000.0000 – 87.4FFF.FFFF 0.25 21174 main CSRs 87.5000.0000 – 87.5FFF.FFFF 0.25 21174 memory control CSRs 87.6000.0000 –...
  • Page 69 Address Map Table A–2 Physical Address Map (Byte/Word Mode Enabled) (Sheet 2 of 2) 21164 Address Size (GB) Selection 87.6000.0000 – 87.6FFF.FFFF 0.25 21174 PCI address translation 87.7000.0000 – 87.7FFF.FFFF 0.25 Reserved 87.8000.0000 – 87.8FFF.FFFF 0.25 21174 miscellaneous CSRs 87.9000.0000 – 87.9FFF.FFFF 0.25 21174 power management CSRs 87.A000.0000 –...

  • Page 70: Address Map

    Address Map The 21164 address space is divided into two regions using physical address <39>: • 0 – 21164 access is to the cached memory space. • 1 – 21164 access is to noncached space. This noncached space is used to access memory-mapped I/O devices.

  • Page 71: Address Space Overview

    Address Map Figure 1–1 Address Space Overview 21164 Environment Main System Memory PCI Window Memory Space 21164 Device Device PCI I/O Space Configuration CSRs Space DMA access to the system memory is achieved using windows in one of the follow- ing three ways: •...

  • Page 72: Pci Address Space

    PCI Address Space Figure 1–2 Memory Remapping 21164 CPU Cached Memory Space (8GB) PCI Memory Space Page PCI Window Direct Map PCI Window Scatter-Gather LJ-05396.AI4 1.2 PCI Address Space The system generates 32-bit PCI addresses but accepts both 64-bit address (DAC cycles and 32-bit PCI address (SAC ) cycles.

  • Page 73: 21164 Address Space

    21164 Address Space 1.3 21164 Address Space Figure 1–3 shows an overview of the 21164 address space. Figure 1–4 shows how the 21164 address map translates to the PCI address space and how PCI devices access the 21164 memory space using DMA transactions. The PCI memory space is double mapped via dense and sparse space.
  • Page 74 21164 Address Space Figure 1–3 21164 Address Space Configuration 21164 Memory Space Scatter-Gather Cached Memory Direct Translation PCI Windows Reserved PCI Memory Space PCI Memory Dense Space PCI I/O Space PCI Memory Sparse Space PCI I/O Space 21164 Programmed I/O DMA Read/Write LJ-05397.AI4 System Address Space...
  • Page 75 21164 Address Space Figure 1–4 21164 and DMA Read and Write Transactions Physical Size Address 000XX 00.0000.0000 8GB Cached Memory 01.FFFF.FFFF 02.0000.0000 Reserved 0=Cached Memory Space 7F.FFFF.FFFF 00XXX 80.0000.0000 PCI Memory 83.FFFF.FFFF Sparse Space 0100X 84.0000.0000 704MB Maximum 84.FFFF.FFFF 01010 85.0000.0000 1=Noncached 01011...

  • Page 76: System Address Map

    21164 Address Space A.3.1 System Address Map Figure 1–5 shows the following system address regions: • Main memory address space contains 8GB. All transactions contain 64 bytes, are cache-block aligned, and are placed in cache by the 21164. Both Istream and Dstream transactions access this address space.

  • Page 77: System Address Map

    21164 Address Space Figure 1–5 System Address Map Main Memory — 8GB 34 33 Memory Address PCI Sparse Memory Space — 512MB Region 1 34 33 PCI Memory Address <28:2> Size PCI Sparse Memory Space — 128MB Region 2 34 33 32 2 1 0 PCI Memory Address <26:2>...

  • Page 78: 21164 Byte/Word Pci Space

    21164 Byte/Word PCI Space Figure 1–6 21174 CSR Space PCI Configuration Space 34 33 32 28 27 2 1 0 Address Size Space CPU Address Size (GB) Contents PCI Configuration Space PCI IACK/Special Cycle 0.25 21174 Main CSRs 0.25 Main Memory Control CSRs 0.25 21174 Address Translation 0.25...

  • Page 79: Byte/Word Pci Space

    21164 Byte/Word PCI Space Figure 1–7 Byte/Word PCI Space PCI Memory Space — 4GB 35 34 33 32 2 1 0 1 Size PCI Memory Address <31:2> PCI I/O Space — 4GB 35 34 33 32 1 Size PCI I/O Address PCI Type 0 Configuration Space —...

  • Page 80: 21164 Size Field

    21164 Byte/Word PCI Space Table 1–3 shows noncached 21164 addresses when byte/word support is enabled. Table A–3 21164 Byte/Word Addressing int4_valid addr_h Instruction <38:37> <3> <2> <1> <0> INT8 — — — addr_h<3:2> — Undefined — LDWU addr_h<3:1> — — Undefined LDBU addr_h<3:0>...

  • Page 81: Cacheable Memory Space

    Cacheable Memory Space 1.5 Cacheable Memory Space Cacheable memory space is located in the range 00.0000.0000 to 01.FFFF.FFFF. The 21174 recognizes the first 8GB to be in cacheable memory space. The block size is fixed at 64 bytes. Read and flush commands to the 21164 caches occur for DMA traffic.
  • Page 82 PCI Dense Memory Space • The concept of dense space (and sparse space) is applicable only to a 21164-gen- erated address. There is no such thing as dense space (or sparse space) for a PCI generated address. • Byte or word transactions are not possible in dense space. The minimum access granularity is a longword on write transactions and a quadword on read transac- tions.

  • Page 83: Pci Sparse Memory Space

    PCI Sparse Memory Space Figure 1–8 shows dense-space address generation. Figure 1–8 Dense-Space Address Generation 21164 Address 39 38 34 33 32 31 05 04 02 01 00 <31:5> int4_valid 21164 05 04 02 01 00 PCI Dense Memory Address LJ04264A.AI4 The following list describes address generation in dense space: •...

  • Page 84: Hardware Extension Register (Hae_Mem

    PCI Sparse Memory Space A.7.1 Hardware Extension Register (HAE_MEM) In sparse space, addr_h<7:3> are used to encode byte enable bits, size bits and the low-order PCI address, ad<2:0>. This means that there are now five fewer address bits available to generate the PCI physical address. The system provides three sparse-space PCI memory regions and allows all three sparse-space regions to be relocated by way of bits in the HAE_MEM register.

  • Page 85: Int4_Valid And 21164 Address Relationship

    PCI Sparse Memory Space • Hardware does not perform read-ahead (prefetch) transactions in sparse space because read-ahead transactions may have detrimental side effects. • Programmers are required to insert memory barrier (MB) instructions between sparse-space transactions to prevent collapsing in the 21164 write buffer. How- ever, this is not always necessary.

  • Page 86: Pci Memory Sparse-Space Read/Write Encodings

    PCI Sparse Memory Space Table 1–6 defines the low-order PCI sparse memory address bits. Signals addr_h<7:3> are used to generate the length of the PCI transaction in bytes, the byte enable bits, and ad<2:0>. The 21164 signals addr_h<30:8> correspond to the quad- word PCI address and are sent out on ad<25:3>.

  • Page 87: Pci Memory Sparse-Space Address Generation - Region

    PCI Sparse Memory Space The high-order ad<31:26> are obtained from either the hardware extension register (HAE_MEM) or the 21164 address depending on sparse-space regions, as shown in Table 1–7. See the Digital Semiconductor 21174 Core Logic Chip Technical Refer- ence Manual for more information about the 21174 HAE_MEM CSR. Table 1–7 PCI Address Mapping 21164 Address...

  • Page 88: Pci Memory Sparse-Space Address Generation - Region

    PCI Sparse Memory Space Figure 1–10 shows the mapping for region 2. Figure 1–10 PCI Memory Sparse-Space Address Generation – Region 2 21164 Address 34 33 32 31 05 04 03 02 39 38 PCI QW Address int4_valid 21164 HAE_MEM CSR Length in Bytes Byte Offset 27 26...

  • Page 89: Pci Sparse I/O Space

    PCI Sparse I/O Space 1.8 PCI Sparse I/O Space The PCI sparse I/O space is divided into two regions — region A and region B. Region A addresses the lower 32MB of PCI I/O space and is never relocated. This region will be used to address the (E)ISA devices.

  • Page 90: Pci Sparse I/O Space Read/Write Encodings

    PCI Sparse I/O Space Table 1–8 contains the PCI sparse I/O space read/write encodings. Table 1–8 PCI Sparse I/O Space Read/Write Encodings Size Byte Offset 21164 Data-In Register addr_h Instruction PCI Byte Byte Lanes addr_h<4:3> <6:5> Allowed ad<2:0> Enable 63..32 31..0 A<7>...

  • Page 91: Pci Sparse I/O Space Address Translation (Region A, Lower 32Mb)

    PCI Sparse I/O Space Figure 1–12 PCI Sparse I/O Space Address Translation (Region A, Lower 32MB) 21164 Address 34 33 32 31 30 29 05 04 03 02 39 38 0 1 1 0 int4_valid 21164 Length in Bytes Byte Offset 25 24 02 01 00 0 0 0 0 0 0 0...

  • Page 92: Pci Configuration Space

    PCI Configuration Space 1.9 PCI Configuration Space The PCI configuration space is located in the range 87.0000.0000 to 87.1FFF.FFFF. Software is advised to clear PYXIS_CTRL<FILL_ERR_EN> when probing for PCI devices by way of configuration space read transactions. This will prevent the 21174 from generating an ECC error if no device responds to the configuration cycle (and random data is picked up on the PCI bus).

  • Page 93: Pci Configuration Space Definition (Sparse)

    PCI Configuration Space Figure 1–14 PCI Configuration Space Definition (Sparse) CPU Address 29 28 21 20 16 15 13 12 07 06 05 04 03 02 Length Byte Offset CFG<1:0> 11 10 02 01 00 Type 0 PCI Configuration IDSEL Function Register Address...

  • Page 94: Cpu Address To Idsel Conversion

    PCI Configuration Space Peripherals are selected during a PCI configuration cycle if the following three con- ditions are met: 1. Their IDSEL pin is asserted. 2. The PCI bus command indicates a configuration read or write. 3. Address bits <1:0> are 00. Address bits <7:2>...

  • Page 95: Pci Configuration Space Read/Write Encodings

    PCI Configuration Space Note: If a quadword access is specified for the configuration cycle, then the least significant bit of the register number field (such as ad<2>) must be zero. Quadword transactions must access quadword aligned registers. If the PCI cycle is a configuration read or write cycle but the ad<1:0> are 01 (that is, a type 1 transfer), then a device on a hierarchical bus is being selected via a PCI-to- PCI bridge.

  • Page 96: Pci Bus Hierarchy

    PCI Configuration Space archically behind it. If the bus number of the configuration cycle matches the bus num- ber of the bridge chip’s secondary PCI interface, it will accept the configuration cycle, decode it, and generate a PCI configuration cycle with ad<1:0> = 00 on its secondary PCI interface.

  • Page 97: Pci Special/Interrupt Cycles

    PCI Special/Interrupt Cycles 1.10 PCI Special/Interrupt Cycles PCI special/interrupt cycles are located in the range 87.2000.0000 to 87.3FFF.FFFF. The Special cycle command provides a simple message broadcasting mechanism on the PCI. The Intel processor uses this cycle to broadcast processor status; but in gen- eral it may be used for logical sideband signaling between PCI agents.

  • Page 98: Pci To Physical Memory Address

    PCI to Physical Memory Address The address space here is a hardware-specific variant of sparse-space encoding. For the CSRs, addr_h<27:6> specifies a longword address where addr_h<5:0> must be zero. All the 21174 registers are accessed with a LW granularity. For more specific details on the 21174 CSRs, see the Digital Semiconductor 21174 Core Logic Chip Technical Reference Manual.

  • Page 99: Pci Target Window Mask Register Fields

    PCI to Physical Memory Address Table A–12 shows the PCI target window mask fields. Table A–12 PCI Target Window Mask Register Fields PCI_MASK<31:20> Size of Window Value of n 0000 0000 0000 0000 0000 0001 0000 0000 0011 0000 0000 0111 0000 0000 1111 16MB 0000 0001 1111...
  • Page 100 PCI to Physical Memory Address The window base address must be on a naturally aligned boundary address depend- ing on the size of the window . This rule is not particularly difficult to obey, because the address space of any PCI device can be located anywhere in the PCI’s 4GB mem- ory space, and this scheme is compatible with the PCI specification: A PCI device specifies the amount of memory space it requires via the Base reg- isters in its configuration space.

  • Page 101: Pci Dma Addressing Example

    PCI to Physical Memory Address Figure 1–17 PCI DMA Addressing Example 21164 System PCI Device's DMA Memory Space Page Scatter-Gather PCI Memory Device 0 Device 1 Device 2 Space (4GB) 21164 Memory Space (8GB) LJ-05402.AI4 Figure 1–18 shows the PCI window logic. The comparison logic associated with ad<63:32>...

  • Page 102: Pci Target Window Compare

    PCI to Physical Memory Address Figure 1–18 PCI Target Window Compare PCI Address n n-1 20 19 Target Hit (Window 3 Only) Compare & Zero Hit Window 3 Window Hit Logic Detect Hit Window 2 Hit Logic Hit Window 1 Hit Window 0 W_DAC Window Enable (WENB)

  • Page 103: Direct-Mapped Addressing

    Direct-Mapped Addressing 1.13 Direct-Mapped Addressing The target address is translated by direct mapping or scatter-gather mapping as deter- mined by the Wx_BASE_SG (scatter-gather) bit of the window’s PCI base register. If the Wx_BASE_SG bit is clear, the DMA address is direct mapped, and the trans- lated address is generated by concatenating bits from the matching window’s trans- lated base register (T_BASE) with bits from the incoming PCI address.

  • Page 104: Scatter-Gather Addressing

    Scatter-Gather Addressing Table A–13 Direct-Mapped PCI Target Address Translation (Sheet 2 of 2) W_MASK<31:20> Size of Window Translated Address <32:2> 0111 1111 1111 Translated Base<33:31> : ad<30:2> 1111 1111 1111 Translated Base<33:32> : ad<31:2> Otherwise Not supported — 1.14 Scatter-Gather Addressing If the Wx_BASE_SG bit of the PCI base register is set, then the translated address is generated by a lookup table.

  • Page 105: Scatter-Gather Pte Format

    Scatter-Gather Addressing Each scatter-gather map page table entry (PTE) is a quadword and has a valid bit in bit position 0, as shown in Figure 1–19. Address bit 13 is at bit position 1 of the map entry. Because the 21174 implements valid memory addresses up to 16GB, then bits <63:22>...

  • Page 106: Scatter-Gather Tlb

    Scatter-Gather TLB Table A–14 Scatter-Gather Mapped PCI Target Address Translation (Sheet 2 of 2) Size of SG W_MASK<31:20> Map Table Translated Address <32:2> 0000 0001 1111 32KB Translated Base<33:15> : ad<24:13> 0000 0011 1111 64KB Translated Base<33:16> : ad<25:13> 0000 0111 1111 128KB Translated Base<33:17>...

  • Page 107: Scatter-Gather Associative Tlb

    Scatter-Gather TLB Figure 1–20 Scatter-Gather Associative TLB Address 8KB CPU Page Address Cycle <31:15> D A T A PCI Address<14:13> Memory Page Address<32:13> Address<12:2> Physical Memory Index Dword Address LJ04276A.AI4 Each time an incoming PCI address hits in a PCI target window that has scatter- gather translation enabled, ad<31:15>...

  • Page 108: Scatter-Gather Tlb Hit Process

    Scatter-Gather TLB mapping. Both paths are indicated — the right side shows the path for a TLB hit, while the left side shows the path for a TLB miss. The scatter-gather TLB is shown in a slightly simplified, but functionally equivalent form. A.15.1 Scatter-Gather TLB Hit Process The process for a scatter-gather TLB hit is as follows: 1.

  • Page 109: Scatter-Gather Map Translation

    Scatter-Gather TLB Figure 1–21 Scatter-Gather Map Translation 40 39 32 31 20 19 0000000000000000000 Offset Window Compare Logic ad_h<31:13> sent to TLB for PCI window W_DAC XXXXX Wn_BASE "hit." DAC indicator 00000000 11111 Wn_MASK also sent. n-10 n-11 000000000 Tn_BASE Tn_BASE Select n-10 n-11...

  • Page 110: Suggested Use Of A Pci Window

    Suggested Use of a PCI Window 1.16 Suggested Use of a PCI Window Figure 1–22 shows the PCI window assignment after power is turned on (configured by firmware), and Table A–15 lists the details. PCI window 0 was chosen for the 8MB to 16MB EISA region because this window incorporates the mem_cs_l logic.

  • Page 111: Peripheral Component Architecture Compatibility Addressing And Holes

    Suggested Use of a PCI Window Table A–15 lists the PCI window power-up configuration characteristics. Table A–15 PCI Window Power-Up Configuration PCI Window Assignment Size Comments Scatter-gather Not used by firmware; mem_cs_l disabled Direct-mapped Mapped to 0GB to 1GB of main memory Disabled —...
  • Page 112 Suggested Use of a PCI Window This mem_cs_l range in Figure 1–23 is subdivided into several portions (such as the BIOS areas) that are individually enabled/disabled using CSRs as listed here: • The MCSTOM (top of memory) register has a 2MB granularity and can be pro- grammed to select the regions from lMB up to 512MB.
  • Page 113 Suggested Use of a PCI Window Note: For more detail, please refer to the Intel 82378 System I/O Manual. As shown in Figure 1–24, PCI window 0 in the 21174 can be enabled to accept the mem_cs_l signal as the PCI memory decode signal. With this path enabled, the PCI window hit logic simply uses the mem_cs_l signal.

  • Page 114: Supporting Products

    Dual inline memory modules (DIMMs) are available from the following sources: Samsung Semiconductor Inc. 3566 North First St. San Jose, CA 95134 USA Phone: 1-408-544-4322 Table B–1 Samsung DIMM Part Number List Size Part Number (# of Bank) Width 16MB...

  • Page 115: Visiontek Dimm Part Number List

    Memory Phone: 847-360-7500 Fax: 847-360-7403 Table B–2 VisionTek DIMM Part Number List Size Part Number Width 16MB VT16455.0 72bit 64MB VT164.0 72bit 128MB VT164V6.0 72bit Viking Components 11 Columbia Laguna Hills,Ca 92656 Phone: 800-338-2361 Fax : 408-643-7250 Table B–3 Viking Components DIMM Part Number List Size Part Number Width...

  • Page 116: Thermal Products

    Fax: 603-642-5819 PN 70-32810-02 B.3 Power Supply An ATX form-factor power supply, suitable for use with the AlphaPC 164UX (+3.3 V, +5 V, –5 V, +12 V, –12 V), is available from: Emacs Electronics USA, Inc. 1410 Gail Borden Place C-4...
  • Page 117 Enclosure B.4 Enclosure An enclosure, suitable for housing the AlphaPC 164UX and its power supply, is available from: Axxion 11 B Leigh Fisher El Paso,Tx. 79906 Phone: 915-772-0360 Fax: 915-778-3200 PN: DL17 Addtronics Industrial 43263 Osgood Road Fremont, Ca 94539...
  • Page 118 Samsung Semicondcutor World Wide Web Internet site: http://www.samsungsemi.com You can also call or e-mail to Samsung CPU Marketing Team. Please use the follow- ing information lines for support.Samsung Alpha Products For documentation and general information:...
  • Page 119 To order the AlphaPC 164UX motherboard, contact your local distributor. The fol- lowing tables list some of the semiconductor products available from Samsung Elec- tronics. Chips Order Number Samsung Electronics 21164 Alpha microprocessor (466 MHz) KP21164-466CN Samsung Electronics 21164 Alpha microprocessor (500 MHz)
  • Page 120 MB164LX-TM1 AlphaPC 164LX Motherboard Windows NT User’s Manual MB164LX-UM2 AlphaPC 164UX/BX Motherboard Technical Reference Manual MB164UX/BX-TM1 AlphaPC 164UX/BX Motherboard Windows NT User’s Manual MB164UX/BX-UM1 You can order the following associated documentation directly from the vendor. Title Vendor Alpha AXP Architecture Reference Manual Call your local distributor or call PN EY–T132E–DP...
  • Page 121 Title Vendor PCI Local Bus Specification, Revision 2.1 PCI Special Interest Group PCI Multimedia Design Guide, Revision 1.0 U.S. 1–800–433–5177 PCI System Design Guide International 1–503–797–4207 PCI-to-PCI Bridge Architecture Specification, 1–503–234–6762 Revision 1.0 PCI BIOS Specification, Revision 2.1 82420/82430 PCIset ISA and EISA Bridges Intel Corporation (includes 82371SB) Literature Sales...

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