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3. TECHNICAL BRIEF
64POLY MIDI
B4
_MIDI_RST
_RST
C212
1000p
G5
13MHZ
CLKI
D2
I2S_SCK
BLCK
D3
I2S_WS
LRCK
D1
I2S_SDO
SDI
D6
GPIO0
C5
GPIO1
C1
GPIO2
C4
GPIO3
B1
LED2_GPIO5
C2
LDE1_GPIO4
C3
LED0
B2
MTR
1V8_VOD
3V0_VOD
VBAT
R222
0
C226
C229
C227
C230
C231
C232
C228
0.1u
1u
0.1u
1u
1u
0.1u
22u
CPU INTERFACE
CPU interface is an 8-bit parallel.
4 control signal(/wr,/rd,/cs,A0 pin), 8 data bit(D0 to D7), and 1 interrupt pin(/IRQ), totaling 13 pins are
connected to the external CPU. This block controls the writing and reading of data by the input polarity of
control signal
INTERFACE REGISTER
This registeris able to access directly ffrom the external CPU. There are 2 bytes spaces. The Intermediate
register can be accessed through the interface register.
INTERMEDIATE REGISTER
This register is accessed through the Interface register.
It is composed to access a latter control register and ROM/SRAM through Intermediate register. This
register is called "Intermediate register" since this exists in the middle of the interface register and the
Control register. In the Intermediate register, there are some registers to control various functions.
C202
C201
120p
120p
R202
R204
68K
68K
R203
R201
68K
68K
C203 0.1u
R205
30K
SPK_P_SM
R207
0
C204
0.1u
R208
30K
C205
R210
R209
33K
33K
1000p
R211
C206
0.022u
3.3K
SPOUT2L
SPOUT1L
SPOUT2R
SPOUT1R
U201
YMU787
TXOUT
EXTOUT
EXC
BBL
HPOUTL
BBR
HPOUTR
C233
C234
0.1u
1u
Figure 3-24. YMU787 CIRCUIT DIAGRAM
- 44 -
C210
470p
B8
R213
3.3
B7
H8
C215
J8
470p
C216
C217
C218
C219
E8
R218
47p
47p
47p
47p
3.3
D7
G7
E6
C8
R220
NA
MIDI_ABB_L
E7
Close to SPEAKER
C221
0
MIDI_HP_L
C7
C222
0
MIDI_HP_R
R221
NA
MIDI_ABB_R
C223
C224
C225
0.1u
0.1u
1u
3V0_VOD
C235
1u
U202
MAX4684EBC_T
C4
C2
MIDI_HP_R
HEADSET_PATH_SEL
NO1
IN1
A4
A2
MIDI_HP_L
NO2
IN2
C1
C3
AUX_OUT_R
NC1
COM1
AUX_SPK_R
A1
A3
AUX_OUT_L
AUX_SPK_L
NC2
COM2
R223
100K
L_SPK_N
L200
27nH
L_SPK_N
L_SPK_P
L202
27nH
L_SPK_P
R_SPK_N
L204
27nH
R_SPK_N
R_SPK_P
L206
27nH
R_SPK_P
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