Gateway FPD 1500 Service Manual page 22

MC68HC705BD1A
28
1
BLOCK DIAGRAM
PA0/PWM8
PA1/PWM9
PA2/PWM10
PA3/PWM11
PA4/PWM12
PA5/PWM13
PA6/PWM14
PA7/PWM15
SDA/PC0/PWM6***
SCL/PC1/PWM7***
PC2/CLAMP
PC3/HSYNCO
PC4/VSYNCO
PC5/AD0
PB1/PWM1**
PB0/PWM0**
SCL/PC1/PWM7***
SDA/PC0/PWM6***
IRQ /VPP
PA7/PWM15
PA6/PWM14
PA5/PWM13
PA4/PWM12
EXTALXTAL
OSCILLATOR
AND DIVIDE
BY 2
PORT DATA
A REG DIR
REG
CPU CONTROL
CPU REGISTERS
DDC12AB/
IIC
0
COND CODE REG 1 1 1
DATA
PORT
DIR
C REG
REG
3.75K/7.75K bytes
ROM
for HC05BD1A
(7.75K bytes for
HC705BD1A)
HCMOS Microcontroller
1
2
RESET
3
VDD
4
VSS
5
6
XTAL
MC68HC(7)05BD1A
EXTAL
7
28-PIN DIP
8
9
10
11
12
13
14
PIN CONFIGURATION
VDD
VSS
RESET IRQ/VPP
CORE
TIMER
(COP)
ALU
68HC05 CPU
ACCUM
INDEX REG
STK PTR
0 0 0 0 0 0 0 1 1
PROGRAM COUNTER
H I N Z C
128/256 bytes
RAM
(256 bytes for
HC705BD1A)
VSYNC
28
HSYNC
27
26 PB2/PWM2**
PB3/PWM3**
25
PC2/CLAMP
24
PB4*/PWM4*
23
PB5*/PWM5*
22
21 PC3/HSYNCO
20 PC4/VSYNCO
19 PC5/AD0
18 PA0/PWM8
17 PA1/PWM9
16 PA2/PWM10
15 PA3/PWM11
PB0/PWM0**
Pulse
PB1/PWM1**
Width
Modulation
PB2/PWM2**
(PWM)
PB3/PWM3**
PB4*/PWM4*
PB5*/PWM5*
6-bit ADC
HSYNC
SYNC
PROCESSOR
VSYNC