Block Diagram - Changer Unit (Cd Section (2/2)) - Sony XES-Z50 Service Manual

7-7. BLOCK DIAGRAM – CHANGER UNIT (CD Section (2/2)) –
DATA, BCLK DATA
1
(Page 84)
BCLK
LRCK, WDCK LRCK
6
(Page 84)
WDCK
GTOP,
RFCK, RAOF GTOP
2
(Page 84)
RFCK
RAOF
C16M
(Page 84) 3
WFCK
SCOR
CDRST
7
(Page 84)
DATA, CLK
8
(Page 84)
WFCK, SCOR,
EXCK, SBSO
5
(Page 84)
25 46
05
D-RAM CONTROLLER
IC401
DIGITAL D OUT
OUT
DATAI
10
DATA
DIGITAL
BCKI
D/A
9
SIGNAL BCK
CONVERTER
SELECTOR
LRCI
PROCESSOR
11 LRCK
INTERFACE
INTERFACE
WDCI
13
D-RAM INTERFACE
TIMING XTAI
GTOP
8
GENERATOR
RFCK
7
READ/WRITE
XROI
6 BASE
COUNTER
C4M
DATA
5
LINKING
WFCK
3 CONTROL
SCOR
VWA
80
GRSRST A0 – A9
1
GRSCOR
79
ADDRESS
MONITOR
CPU INTERFACE
D1 – D4
2
XRST
61 62 64 74 60 58 59 63
XRAS
XCAS
XWE
XWE2
XOE
XOE2
28 24 26 22 23 27
SYSTEM CONTROLLER
IC301 (2/3)
4 47
38 39 31
X301
6 5
8MHz
TH301 TH302
EEPROM
IC302
– 85 –
26
DATA
24
BCK
23
LRCK
25
CLOCK
BUFFER
16 GENERATOR
IC504
IC503
D-RAM
IC402
A0 – A9 D1 – D4
9 – 12, 14 – 18, 5 1, 2, 24, 25 23 4 3 22
OE1
WE1
ADDRESS BUS
RAS
CAS
WE2
DATA BUS
OE2
9 – 12, 14 – 18, 5 1, 2, 24, 25 23 4 3 22
A0 – A9 D1 – D4
RAS
36
CAS
45
D-RAM
WE1
37
IC403
WE2
38
OE1
46
OE2
47
CD TEXT DECODER
IC303
SBSO
9 SSI
EXCK
8 SCLK
WFCK
WFCK
77
SCOR
76 SCOR
29 EXTAL
X302
10MHz
30 XTAL
CSO 49 6
CSI
7
CSI 50 CSO
CCLK 48 5 CCLK
45 4
REQ REQ
44
BUSY 56 BUSY
D303
RSTO 43 28 RST
WE 63
CE 62
RESET 30
BU. CHECK
64 78 BUCK
32
RESET SIGNAL
+5V GENERATOR
IC903
• Signal path.
: CD PLAY
DATA,
BCK, LRCK
9 (Page 87)
SYNC (44.1kHz)
10
(Page 87)
S-RAM
IC304
29 WE
22 CE1
30
CE2
24 OE
+5V
BATTERY CHECK
11 (Page 93)
RST
12 (Page 93)
– 86 –
XES-Z50