Sony PRS-505 Service Manual page 42

PRS-505
QQ
3 7 63 1515 0
Pin No. Pin Name
K5 NVDD1
K6, K7 VSS
K8 NVDD1
K9 VSS
K10 D1
K11 BOOT2
K12 TDI
K13 BIG_ENDIAN
K14 XRESET-OUT
K15 XTAL32K
L1, L2 A10, A9
L3, L4 D17, D18
L5, L6 NVDD1
L7 XCS5
L8 D2
L9 PA20
L10, L11 VSS
L12 POR
L13 VSS
L14 XTAL16M
L15 EXTAL32K
M1 D16
M2 to M4 D15, D13, D10
TE
L 13942296513
M5 XEB3
M6 NVDD1
M7, M8 XCS4, XCS1
M9 PA18
M10 XRW
M11 VSS
M12 BOOT3
M13 QVDD2
M14 XRESET-IN
M15 EXTAL16M
N1, N2 A8, A7
N3 D12
N4 XEB0
N5, N6 D9, D8
N7, N8 XCS3, XCS0
N9 PA17
N10 D0
N11, N12 DQM2,DQM0
N13 SDCK0
N14 TRISTATE
N15 XTRST
P1 D14
www
P2 A1
P3 to P6 A2 to A5
.
P7, P8 D6, D5
P9, P10 MA10, MA11
42
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I/O
- Power supply terminal (+2.9V)
- Ground terminal
- Power supply terminal (+2.9V)
- Ground terminal
Two-way data bus with the memory stick duo/SD memory card controller, USB controller,
I/O
NAND fl ash memory, SD-RAM and NOR fl ash memory
I System boot mode select signal input terminal
I Test data input terminal
I Not used
Reset signal output to the audio D/A converter, memory stick duo/SD memory card control-
O
ler, USB controller, NAND fl ash memory and NOR fl ash memory
O System clock output terminal (32.768 kHz)
Address signal output to the memory stick duo/SD memory card controller, SD-RAM and
O
NOR fl ash memory
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+2.9V)
O Chip select signal output terminal
Two-way data bus with the memory stick duo/SD memory card controller, USB controller,
I/O
NAND fl ash memory, SD-RAM and NOR fl ash memory
O Not used
- Ground terminal
I Power on reset signal input from the sub CPU
- Ground terminal
O System clock output terminal
I System clock input terminal (32.768 kHz)
I/O Two-way data bus with the SD-RAM
Two-way data bus with the memory stick duo/SD memory card controller, USB controller,
I/O
SD-RAM and NOR fl ash memory
O Byte strobe signal output terminal
- Power supply terminal (+2.9V)
O Chip select signal output terminal
- Not used
O Read/write enable signal output terminal
- Ground terminal
I System boot mode select signal input terminal
- Power supply terminal (+1.9V)
I Master reset signal input from the sub CPU
I System clock input terminal
Address signal output to the memory stick duo/SD memory card controller, USB controller,
O
SD-RAM and NOR fl ash memory
Two-way data bus with the memory stick duo/SD memory card controller, USB controller,
I/O
SD-RAM and NOR fl ash memory
O Byte strobe signal output terminal
Two-way data bus with the memory stick duo/SD memory card controller, USB controller,
I/O
SD-RAM and NOR fl ash memory
O Chip select signal output terminal
- Not used
Two-way data bus with the memory stick duo/SD memory card controller, USB controller,
I/O
NAND fl ash memory, SD-RAM and NOR fl ash memory
O Data enable signal output to the SD-RAM
O Clock enable signal output to the SD-RAM
I Not used
I Test reset signal input terminal
Two-way data bus with the memory stick duo/SD memory card controller, USB controller,
I/O
SD-RAM and NOR fl ash memory
Address signal output to the memory stick duo/SD memory card controller, USB controller
O
and NOR fl ash memory
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y
Address signal output to the memory stick duo/SD memory card controller, USB controller,
O
SD-RAM and NOR fl ash memory
i
Two-way data bus with the memory stick duo/SD memory card controller, USB controller,
I/O
NAND fl ash memory, SD-RAM and NOR fl ash memory
O Address signal output to the SD-RAM
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2 9
8
Description
Not used
"H": reset
Not used
Q Q
3 6 7 1 3 1 5
Not used
"L": reset
Not used
Not used
Not used
co
.
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9