Sony CDX-V3800 Service Manual page 29

• IC400 SPCA717A-HL211 (VIDEO SIGNAL PROCESSOR) (SERVO BOARD (2/2))
Pin No. Pin Name
1 FSADJUST
2 COMP
3 AVCC
4 VREF OUT
5 VREF IN
6 VBIAS
7 NC
8 AGND
9 SLEEP
10 SVIDEO
11 CBSWAP
12 MASTER
13 MODEA
14 MODEB
15 CLK
16 XTALO
17 to 24 P0 to P7
25 CLKOUT
26 DGND
27 VDD
28 VSYNC
29 HSYNC
30 TEST
31 AGND
32 CVBSY
I/O
Full-Scale adjust control pin The Full-Scale current of D/A converters can be
—
adjusted by connecting a resistor (RESET) between this pin and ground.
Compensation pin A0.1 µF ceramic capacitor must be used to bypass this pin to VAA.
—
The lead length must be kept as short as possible to avoid noise.
— Analog power supply pin (+3.3 V)
Voltage reference signal output It generates typical 1.2 V voltage reference and may
O
be used to drive pin 5 (VREF IN) directly.
Voltage reference signal input An external voltage reference must supply typical
1.235 V to this pin. A0.1 µF ceramic capacitor must be used to de-couple this input
I
to ground. The decoupling capacitor must be as closed as possible to minimize the
length of the load. The pin may be connected derectry to pin 4 (VREF OUT).
— DAC bias voltage Potential normally 0.7 V less than pin 2 (COMP).
— Not used. (Open)
— Analog ground pin
Power save mode A logic high on this pin puts the chip into power-down mode. This
I pin is equal to reset pin. An external logic high pulse should input to the pin when
power on.
Video signal selection pin A logic high selects Y output. A logic low selects
I
composite video output. Not used in this set. (Fixed at "L".)
Cr and Cb pixel sequence configuration pin A logic high swap the Cr and Cb sequence.
I
Not used in this set. (Fixed at "L".)
Master/Slave mode selection A logical high for master mode operation. A logical 0
I
for slave mode operation. Not used in this set. (+3.3 V)
I Mode configuration pin Not used in this set. (Fixed at "L".)
I Mode configuration pin
27 MHz crystal oscillator input A crystal with 27 MHz clock frequency can be
I
connected between this pin and pin qh (XTALO).
O Crystal oscillator output Not used in this set. (Open)
YCrCb pixel inputs
I
They are latched on the rising edge of CLK.
O Pixel clock signal output Not used in this set. (Open)
— Digital ground pin
— Digital power supply pin (+3.3 V)
Vertical sync input/output
I/O
VSYNC is latched/output following the rising edge of CLK.
Horizontal sync input/output
I/O
HSYNC is latched/output following the rising edge of CLK.
I Test pin These pins must be connected to digital ground.
— Analog ground pin.
Composite/Luminance output. This is a high-impedance current source output. The
O
output format can be selected by the PAL pin. The CVBSY can drive a 37.5 Ω load.
Pin Description
CDX-V3800
29