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EN 134
9.
BP2.2U, BP2.3U
9.17.6 Diagram B4A, CY2305SC-1 (IC 7J08)
Block Diagram
REF
S2
S1
9.17.7 Diagram B4E, NCP303LSN (IC 7LB0 - 7LB4)
Circuit Descriptions, Abbreviation List, and IC Data Sheets
PLL
MUX
Select Input
Decoding
Figure 9-35 Internal block diagram and pin configuration
Block Diagram
NCP303LSNxxT1
Open Drain Output Configuration
2
Input
V
ref
3
Gnd
Pin Configuration
Reset
1
Output
2
Input
3
Ground
xxx = 302 or 303
Y
W
Figure 9-36 Internal block diagram and pin configuration
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
1
Reset Output
R
D
5
C
D
5
C
D
4
N.C.
= Year
= Work Week
(Top View)
F_15400_133.eps
Pin Configuration
SOIC/TSSOP
Top View
REF
CLKOUT
1
16
CLKA1
2
15
CLKA4
CLKA3
3
14
CLKA2
V
V
4
13
DD
DD
GND
GND
5
12
CLKB4
CLKB1
6
11
CLKB3
7
10
CLKB2
S1
S2
8
9
SOIC
Top View
1
8
CLKOUT
REF
CLK4
2
7
CLK2
V
3
6
DD
CLK1
4
CLK3
GND
5
250505
E_14620_146.eps
200804
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