JVC GZ-MG20EK Schematic Diagrams page 15

MAIN(TG068) SCHEMATIC DIAGRAM
0 1 MAIN(TG068)
TO CCD(CN5001)
CN105
QGF0547C2-24X
REG+CCD 1
REG+CCD 2
REG-CCD 3
REG-CCD 4
CCD_CTL 5
R5514
GND
10
GND
GND
CCD_OUT
GND
GND
GND
RG 13
H1 14
H2 15
SUB 16
R5515 10
V1 17
R5516 10
V2 18
R5517 10
V3 19
R5518 10
V4 20
GND 21
G_RST 22
REG_3.1V 23
P_GYAMP 24
TO P.PRCS
P_GYAMP
REG_3.1V
TO P.PRCS,
G_RST
GYRO
GND
TO DSP CCD_CTL
TO SUB CPU TG2_RST
TO P.PRCS TG_CS
TO CDS,
CAM_CLK
P.PRCS,
CAM_OUT
OP DRV
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
C5510
0.1
36 35 34 33 32 31 30
37 CLK13/CL
38 TEST
39 VM
40 V2
41 V4
IC5501
42 V1
JCY0185
(TG/V_DRIVER)
43 VH
C5514
44 V3
1/35
C5511 C5515
45 SUB
T 0.1 0.1
D5501
46 VL
1SS355-X
47 Vss6
R5511
48 RST
100k
1 2 3 4 5 6 7
C5501
0.1
(No.YF108)2-27
C5508 X5501
NAX0587-001X
0.1
(54MHz_CXO)
OUT GND
VDD CTL
29 28 27 26 25
C5507
0.1
R5510
10
Vdd5 24
CAM/VTR 23
CLK18/MCK 22
R5509
Vss4 21 10
DCC 20
XRS 19
R5508 10
SHD 18
R5507 10
SHP 17
Vdd4(CDS) 16
C5504
Vss3 15
0.1
H2 14
Vss2 13
R5506
10
8 9 10 11 12
C5523
R5512
C5503
0.1
R5519
0Ω
C5502
IC5502
0.1
C5521
C5518
0.1
T
C5519
47/4
2-28(No.YF108)
TO P.PRCS
TG_ID
TL5001
TG_VD
TG_HD
MCLKI
TO CDS
OBCLP
PBLK
ADCLK
L5503
NQR0129-002X
C5505
C5506
10/6.3
T
TO CDS
CDS_3V
SHD
SHP
R5513
C5522 C5526 C5525
5 4 5 4
IC5503
(3.3V_REG) (3.0V_REG)
1 2 3 1 2 3
C5524
GND
REG_4.8V
L5502
CAM_3.1V
NQR0129-002X
L5501
C5520 REG+CCD
10µ
0.1
REG-CCD
y30328001a_rev0.1
TO MAIN IF
(CN101,CN103),CDS
TO MAIN IF,V I/O
TO MAIN IF(CN103)