Sony MZ-R91 Service Manual page 31

• MAIN BOARD IC502 CXD2660GA
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 16M BIT D-RAM)
Pin No. Pin Name
1 VDC0
2 MNT0
3 MNT1
4 MNT2
5 MNT3
6 SWDT
7 SCLK
8 XLAT
9 VSC0
10 SRDT
11 SENS
12 XRST
13 SQSY
DQSY
14
(MTFLGL)
15 RECP
16 XINT
17 TX
18 VDIO0
19 OSCI
20 OSCO
21 VSIO0
22 to 29 NC
30 VSC1
31 XTSL
32 XCS_DSP
33 DIN1
34 DOUT
35 DT72
36, 37 VDC1, VDC2
38 DATAI
39 LRCKI
40 XBCKI
41 ADDT
42 DADT
43 LRCK
44 VSC2
45 XBCK
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
I/O
—
Power supply terminal (+1.8V) (for internal logic)
I/O Not used (open)
O Recording shock detect signal output to the system controller (IC801)
O Off track signal output to the SN761056ADBT (IC501) and system controller (IC801)
Focus OK signal output to the system controller (IC801)
O
"H": is output when focus is on ("L": NG)
I Serial data input from the system controller (IC801)
I (S) Serial clock signal input from the system controller (IC801)
I (S) Serial data latch pulse input from the system controller (IC801)
—
Ground terminal (for internal logic)
O (3) Serial data output to the system controller (IC801)
O (3) Internal status (SENSE) output to the system controller (IC801)
I (S) Reset signal input from the system controller (IC801) "L": reset
Subcode Q sync (SCOR) output the system controller (IC801)
O
"L" is output every 13.3 msec Almost all, "H" is output
Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC801)
O
"L" is output every 13.3 msec Almost all, "H" is output
Laser power selection signal input from the system controller (IC801)
I
"L": playback mode, "H": recording mode
O Interrupt status output to the system controller (IC801)
Recording data output enable signal input from the system controller (IC801)
I
Writing data transmission timing input
—
Power supply terminal (+2.4V) (for I/O)
I System clock (512Fs=22.5792 MHz) input terminal
O System clock (512Fs=22.5792 MHz) output terminal
— Ground terminal (for I/O)
—
Not used (open)
—
Ground terminal (for internal logic)
Input terminal for the system clock frequency setting
I
"L": 45.1584 MHz, "H": 22.5792 MHz (fixed at "H" in this set)
I Chip select signal input from the system controller (IC801)
I Digital audio signal input terminal when recording mode
O Digital audio signal output terminal when playback mode Not used (open)
O Not used (open)
—
Power supply terminal (+1.8V) (for internal logic)
I Serial data input terminal Not used (fixed at "L")
L/R sampling clock signal (44.1 kHz) input terminal
I
"L": Rch, "H": Lch Not used (fixed at "L")
I Serial input/output data bit clock signal (2.8224 MHz) input terminal Not used (fixed at "L")
I
Recording data signal input from the A/D, D/A converter (IC301)
O Playback data signal output to the A/D, D/A converter (IC301)
O L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC301)
—
Ground terminal (for internal logic)
O Serial input/output data bit clock signal (2.8224 MHz) out put to the A/D, D/A converter (IC301)
Description
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