ViewSonic VS11446 Service Manual page 19

Auto-Position
1. Define the RGB color noise margin: When the value of color channel R or G or B is greater than
these noise margins, a valid pixel is found.
2. Define the threshold-pixel for vertical boundary search
3. Define the boundary window of searching for horizontal boundary search.
4. Start auto-function.
5. The result can be read from register.
Auto-Tracking
1. Setting the control-registers for the function (auto-phase, auto-balance) according to the
Control-Table.
2. Define the Threshold
3. Define the boundary window of searching for tracking window.
4. Start auto-function.
5. The result can be read from register
PLL System
Inside the RTD, there are four PLL systems for display clock and ADC sample clock (PLL1,
PLL2,M2PLL, DPLL ).
DCLK PLL
DPLL frequency = F_IN * DPM / DPN * Divider.
F_IN is input crystal frequency. DPM and DPN is in DPLL_M and DPLL_N.
DPLL_N, and it divide PLL frequency by 1, 2, 4 or 8.
According to parameter DPN, you must set LPF Mode in DPLL_WD. If LPF Mode is 1, the charge
pump current, Ich, must be DPM/17.6, while Ich must be DPM/1.67 if LPF Mode is 0. The charge
pump current Ich is in DPLL_CRNT.
Spread-Spectrum function is also build in DCLK to reduce EMI. You can control the SSP_I, SSP_W,
and FMDIV to fine-tune the EMI.
M2PLL is a PLL used to power-on reset, FIFO clock and Internal crystal clock. After power-on reset,
M2PLL output 10 times frequency of crystal clock. According to crystal frequency, set M2PLL to keep
FIFO clock frequency between 240MHz and 250MHz.
ADC Pixel Sampling PLL
The input pixel sampling PLL of RTD compose of PLL1 and PLL2 and DDS, the hybrid PLL system
inherently has a process-independent advantages comparing with pure analog PLL, DDS synthesizer is
in charge of the phase-frequency control, PLL1 provided a high frequency to get a larger bandwidth
letting the system fast locking, PLL2 finally synthesize the desired pixel sampling clock. The block
diagram shown below describes our high-performance tracking system.
Host Interface
Parallel/Serial Port Determination:
After RESET end, the status of pin 5 (TMDS_TST) can be sensed to determine the interface mode:
high for parallel port, low, low for serial port.
Host Interface Location Determination:
After the falling edge of RESET signal, the status of pin 3 can be sensed to determine the host interface
location: high for 112-115,118,119, and low for 52-57
Reset Output
We have the RESET_OUT function, and also reserve the RESET_IN function. By the bounding of
internal pins we can select two kinds of reset function. First of all is only reset-out, we can output the
reset signal to MCU, and the MCU can reset the RTD by firmware. The second is RTD output reset and
also reset itself. Notice that the reset output is positive polarity, besides, the reset output is open-drain
pin, please don't forget to attach a pull-up resistor (10K). The reset function for 3.3V operating
voltage detection is determined by 33VRST_REF voltage, No matter 5V or 3.3V MCU is been used,
divider the input voltage on 33VRST_REF to 2.2V for internal power sensing circuit detecting, the
divider resistor should be 10K level avoiding current leakage.
The Programmable Schmitt Trigger of HSYNC
To get better waveform of the input HSYNC, we have a programmable Schmitt Trigger circuit. For
different HSYNC amplitude and polarity, we can select different setting of the threshold voltage. The
Vt + and the Vt - can be selected by register CR97 We can select the old mode or the new mode. When
using the new mode we can directly determine the positive threshold voltage (1.4V, 1.6V... 2.6V), and
we can choose the hysterias from
the Vt + to determine the Vt - (0.6V, 0.8V, 1.0V, 1.2V). We also can finely tune the voltage by minus
0.1V. For application, we can select different threshold voltage by the polarity of the HSYNC. The
control register is CR97
16
ViewSonic Corporation
VX2235wm-4
Confidential - Do Not Copy